In this paper, a high-speed, scalable on-chip serial transmission design is proposed to provide 2Gb/s transmission bandwidth for SoC applications. By using the dynamic control technology and the single-phase pulse-tri...
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ISBN:
(纸本)0780393457
In this paper, a high-speed, scalable on-chip serial transmission design is proposed to provide 2Gb/s transmission bandwidth for SoC applications. By using the dynamic control technology and the single-phase pulse-triggered TSPC shift register design, we can provide high-speed on-chip serial transmission. Moreover, the shift register design is a scalable design. By using the proposed method, we can provide 3 times wider bandwidth as compared to the prior art design [6].
In order to pre-evaluate the necessary time needed to write a flash cell memory, we use a simplified expression for the Fowler Nordheim injecting current during the erase mode, which allows us to find a relationship b...
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ISBN:
(纸本)0780393457
In order to pre-evaluate the necessary time needed to write a flash cell memory, we use a simplified expression for the Fowler Nordheim injecting current during the erase mode, which allows us to find a relationship between the applied voltages and the resulting threshold voltage. We show in this study that the absolute value of the derivative of the threshold voltage is equal to the positive signal slope applied on the control gate. We validate this assumption by measurements on samples provided by STmicroelectronics.
Low power, high speed arid high flexibility are today's requirements for SoC (System On Chip) designers. Because average bandwidth at the side of main memory is crucial for system performance, our research focuses...
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ISBN:
(纸本)0780393457
Low power, high speed arid high flexibility are today's requirements for SoC (System On Chip) designers. Because average bandwidth at the side of main memory is crucial for system performance, our research focuses on the development of digital architectures for low-level and very high-throughput data processing. Based on an associative computing paradigm, this paper presents the implementation of a scalable associative processor dedicated to textual retrieval in huge databases by means of approximate matching techniques. It exposes the internal architecture of the system and shows an efficient use of pipelining within the scalable and highly parallel processing core. As a key feature to the architecture, the hardware implementation of sorting and merging algorithms based on comparator networks yields very short time for the ranking operations. Moreover, it permits to keep the final processing speed higher enough to reach the maximum peripheral data throughput.
This paper presents a reconfigurable baseband DAC system (current-steering D/A + transimpedance stage + low-pass reconstruction filter) operating in a low-voltage multistandard transmitter, while satisfying high linea...
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ISBN:
(纸本)0780393457
This paper presents a reconfigurable baseband DAC system (current-steering D/A + transimpedance stage + low-pass reconstruction filter) operating in a low-voltage multistandard transmitter, while satisfying high linearity requirements. The implemented block can process the WLAN 802.11a/b/g and the UMTS signals. The device has been integrated in a 0.13 μm CMOS technology and operates with a 1.2V supply voltage. Experimental results show that the proposed circuit achieves a 29.5dBm OIP3 when configured for the WLAN setting, and a 31dBm OIP3 when configured for the UMTS setting. The current consumption, optimized for the two cases, is 16.2mA/14mA for WLAN/UMTS, respectively.
This paper proposes two novel techniques, namely low-voltage Switched-Capacitor Common-Mode Feedback (SC-CMFB) and cross-coupled passive input sampling branch that can be efficiently applied to very low-voltage reset-...
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ISBN:
(纸本)0780393457
This paper proposes two novel techniques, namely low-voltage Switched-Capacitor Common-Mode Feedback (SC-CMFB) and cross-coupled passive input sampling branch that can be efficiently applied to very low-voltage reset- and switched-opamp architectures. The proposed CMFB circuit utilizes the inherent differential-pair of the opamps as the virtual ground common-mode (CM) voltage detector to avoid the traditional problems of floating switches, while the input sampling branch allows the direct passive interface from the external input signal to the 1st stage switched- and reset-opamp circuit, thus providing a new approach for very low-voltage implementation of fully-differential switched- and reset-opamps as well as saving opamps' power. Simulations with real switches and a fully-differential opamp in 1-V supply voltage are provided to verify the effectiveness of the proposed technique.
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