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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

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Meta-Heuristic Optimization of Custom Heterogeneous Blocks defined eFPGA Design 38

Meta-Heuristic Optimization of Custom Heterogeneous Blocks d...

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38th International conference on VLSI Design and International conference on Embedded Systems

作者： Bhargav, D., V Pradyumna, G. Rao, Madhav IIIT Bangalore Bangalore Karnataka India

ISBN: (纸本)9798331522452;9798331522445

Modern Field-Programmable Gate Arrays (fpgas) are highly versatile, with reconfigurable logic functionality that allows designers to create custom designs. Unlike traditional fixed-function integrated circuits, fpgas are reconfigured multiple times to perform different tasks, making them ideal for various applications. An Embedded FPGA (eFPGA) takes the concept of an FPGA and integrates it as an IP core within a larger System-on-Chip (SoC) or Application-Specific Integrated Circuit (ASIC). The proposed work employs Non-dominated Sorting Genetic Algorithm-ii (NSGA-ii) to evolve efficient and high-performing eFPGA architectures with reduced critical path delay and power defined by a sufficient number of Configurable Logic Blocks (CLBs), custom Digital Signal Processors (DSPs) and Block RAM (BRAMs) for targetting workload under consideration. As a result, this work presents a well-balanced eFPGA architecture layout obtained for four workloads equipped with different numbers of heterogeneous and configurable logic blocks. The results showed a significant improvement of 44.62% in hardware parameters.

关键词： eFPGA VTR OpenFPGA NSGA-ii Secure Silicon FPGA Layout reconfigurable computing

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Performance Modeling and Scalability Analysis of Stream computing in ESSPER FPGA Clusters 22

Performance Modeling and Scalability Analysis of Stream Comp...

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22nd International conference on Field Programmable technology (ICFPT)

作者： Miyagi, Ryota Yasudo, Ryota Sano, Kentaro Takase, Hideki Univ Tokyo Tokyo Japan Kyoto Univ Kyoto Japan RIKEN Kobe Hyogo Japan

ISBN: (纸本)9798350359114

ESSPER is a flexible and scalable FPGA cluster system designed for reconfigurable HPC, with customizability, scalability, and interoperability with existing HPC systems. The inherent characteristics of ESSPER make it a superior alternative for achieving highly scalable computing solutions, particularly for compute-intensive applications such as numerical simulations and machine learning. However, constraints in communication bandwidth or latency can impact performance and scalability. This paper builds upon a previous performance model study to analyze performance modeling and scalability of streaming computation using a 1D ring of cascaded fpgas with high-speed, low-latency communication links in ESSPER. For evaluation and verification, we implemented a simple vector addition on ESSPER. The Result indicates that measured performance metrics closely align with predictions from the performance model. This model can also be used to estimate performance for other ESSPER applications.

关键词： streaming computing scalability multiple fpgas high-performance computing.

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Power Aware Scheduling of Tasks on fpgas in Data Centers 32

Power Aware Scheduling of Tasks on FPGAs in Data Centers

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32nd Euromicro International conference on Parallel, Distributed and Network-Based Processing (PDP)

作者： Paul, Rourab Danelutto, Marco Univ Pisa Dept Comp Sci Pisa Italy

ISBN: (纸本)9798350363074;9798350363081

A variety of computing platforms like Field Programmable Gate Array (FPGA), Graphics Processing Unit (GPU) and multicore Central Processing Unit (CPU) in data centers are suitable for the acceleration of data-intensive workloads. FPGA platforms in data centers are significantly gaining popularity for high-performance computations due to their high speed, reconfigurable nature and cost-effectiveness. Heterogeneous, highly parallel computational architectures in data centers and highspeed communication technologies like 5G are becoming increasingly suitable for real-time applications. However, flexibility, cost-effectiveness, high computational capabilities and energy efficiency remain challenging issues in FPGA based data centers. This paper introduces a power-aware scheduling methodology to accommodate execution of periodic hardware tasks within the available fpgas of a data center at their potentially maximum speed. The proposed methodology guarantees the execution of available tasks using the maximum number of parallel computation units (CUs) possible to implement in the fpgas with minimum power consumption. The proposed scheduling methodology is implemented in a data center with multiple Alveo-U50 Xilinx-AMD fpgas and V itis 2023 tool. The evidence from the implementation shows the proposed scheduling methodology is efficient compared to existing solutions.

关键词： Data Center FPGA Scheduling Power

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FPGA Based Hardware Accelerator for Bio-Informatics applications 3

FPGA Based Hardware Accelerator for Bio-Informatics Applicat...

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3rd IEEE Asian conference on Innovation in technology, ASIANCON 2023

作者： Kate, Akash Khurge, Deepti Pimpri-Chinchwad College of Engineering Electronics and Telecommunication Engineering Pune India

ISBN: (纸本)9798350302288

We present the design and implementation of an FPGA-based accelerator for bioinformatics applications in this paper. To process large amounts of data generated by next generation sequencing (NGS) technologies, bioinformatics applications require high-performance computing capabilities. Because of their parallel processing capabilities and reconfigurable hardware, fpgas are a promising solution for accelerating bioinformatics applications. To achieve high throughput and low latency, the proposed accelerator architecture employs parallelism and pipelining. The FPGA accelerator's performance is compared to software implementations on a CPU. The results of the experiments show that the FPGA accelerator outperforms the CPU implementation. © 2023 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Minimizing Area Footprint of UAV Communication Security using fpgas

Minimizing Area Footprint of UAV Communication Security usin...

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4th IEEE Annual International conference on Cyber Security and Resilience (IEEE CSR)

作者： Konstantopoulou, Evangelia Athanasiou, George S. Sklavos, Nicolas Univ Patras Comp Engn & Informat Dept SCYTALE Grp Patras Greece U Blox Athens SA Athens Greece

ISBN: (纸本)9798350375367

Nowadays, unmanned aerial vehicles (UAVs) are used in numerous applications, facilitating human activities. However, UAVs are vulnerable to cyberattacks, particularly concerning communication. To protect UAV communication, lightweight cryptographic algorithms have been enrolled, ensuring security in such resource-constrained environments. The National Institute of Standards and technology (NIST) promoted sponge constructions and non-linear feedback shift registers (NFSR) as the bases for lightweight cryptography. As hardware offers significant advantages regarding performance and area-footprint over software, research moved on employing reconfigurable computing like Field-Programmable Gate Arrays (fpgas) in this field. This paper proposes a novel security realization in UAVs based on hardware implementation of lightweight NFSR-based authenticated encryption, targeting reduced-area and uncompromised security. Xilinx Artix-7 FPGA is considered and NIST lightweight finalist TinyJAMBU mechanism is employed. The area consumption of the proposed solution is minimal, compared to existing solutions in the literature, making it ideal for UAV devices with limited bandwidth and computational resources.

关键词： lightweight cryptography unmanned aerial vehicles (UAVs) hardware optimization FPGA implementation area NIST TinyJAMBU

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Dynamic Security Management of Systems on Chip via Embedded FPGA in 22nm CMOS technology 67

Dynamic Security Management of Systems on Chip via Embedded ...

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67th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Elgendy, Elsayed Ghonem, Ahmed Zaky Abouzeid, Sherif Elsadek, Islam Kevin, Liao Vincent, Yen Yap, K. C. Faith, Brian Tawfik, Eslam Yahya Ohio State Univ Columbus OH 43210 USA QuickL Corp San Jose CA USA

ISBN: (纸本)9798350387186;9798350387179

There has been a rising demand for more efficient and secure processing on the edge to cope with the number of emerging Internet of Things (IoT) applications. These applications scale from low-duty cycles high-performance tasks to high-duty cycle ultralow power operations. Embedded fpgas (efpgas) can address many of these demands given their flexibility compared to ASIC, low latency, and lower energy consumption compared to CPUs. efpgas allow for post-silicon manufacturing patch-ability, adaptive performance, and on-chip control of large SoCs. This paper presents the implementation of eFPGA tailored for secure, efficient, and flexible System-On-Chip (SoC) management. The eFPGA acts as the heart of a Security Management Unit (SMU), which is part of a larger secure SoC platform that combines a True Random Number Generator (TRNG), an AES engine, and a NIST-compliant Lightweight cryptographic engine (LWC). Fabricated on 22nm CMOS technology, the eFPGA was used to dynamically manage the security policies of different IPs in the SoC under a proposed threat model. We report the performance of these applications, showing the benefits the embedded fabric provides.

关键词： Embedded FPGA SoC Security Security Policy Management reconfigurable computing System on a Chip

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VEDLIoT - Next generation accelerated AIoT systems and applications 23

VEDLIoT - Next generation accelerated AIoT systems and appli...

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20th ACM International conference on computing Frontiers (CF)

作者： Mika, Kevin Griessl, Rene Kucza, Nils Porrmann, Florian Kaiser, Martin Tigges, Lennart Hagemeyer, Jens Trancoso, Pedro Azhar, Muhammad Waqar Qararyah, Fareed Zouzoula, Stavroula Menetrey, James Pasin, Marcelo Felber, Pascal Marcus, Carina Brunnegard, Oliver Eriksson, Olof Salomonsson, Hans Odman, Daniel Ask, Andreas Casimiro, Antonio Bessani, Alysson Carvalho, Tiago Gugala, Karol Zierhoffer, Piotr Latosinski, Grzegorz Tassemeier, Marco Porrmann, Mario Heyn, Hans-Martin Knauss, Eric Mao, Yufei Meierhoefer, Franz Bielefeld Univ Bielefeld Germany Chalmers Univ Technol Gothenburg Sweden Univ Neuchatel Neuchatel Switzerland VEONEER Inc Vargarda Sweden EMBEDL AB Gothenburg Sweden Univ Lisbon Lisbon Portugal Antmicro Poznan Poland Osnabruck Univ Osnabruck Germany Univ Gothenburg Gothenburg Sweden Siemens AG Erlangen Germany

ISBN: (纸本)9798400701405

The VEDLIoT project aims to develop energy-efficientDeep Learning methodologies for distributed Artificial Intelligence of Things (AIoT) applications. During our project, we propose a holistic approach that focuses on optimizing algorithms while addressing safety and security challenges inherent to AIoT systems. The foundation of this approach lies in a modular and scalable cognitive IoT hardware platform, which leverages microserver technology to enable users to configure the hardware to meet the requirements of a diverse array of applications. Heterogeneous computing is used to boost performance and energy efficiency. In addition, the full spectrum of hardware accelerators is integrated, providing specialized ASICs as well as fpgas for reconfigurable computing. The project's contributions span across trusted computing, remote attestation, and secure execution environments, with the ultimate goal of facilitating the design and deployment of robust and efficient AIoT systems. The overall architecture is validated on use-cases ranging from Smart Home to Automotive and Industrial IoT appliances. Ten additional use cases are integrated via an open call, broadening the range of application areas.

关键词： Artificial Intelligence of Things (AIoT) Acceleration reconfigurable and Heterogeneous computing Machine Learning (ML) Distributed Attestation and Security

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Lightweight ANU-ii Implementation on FPGA 8

Lightweight ANU-II Implementation on FPGA

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8th IEEE International conference on Distributed computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2024

作者： Shetty, Thrapthi Kiran Kumar, V.G. Khati, Mohan Singh Sandesh Deeptha Suresh, A. Musthafa, Rasim A J Instittue of Engineering and Technology Kottara Department of Electronics and Communication Engineerng Mangaluru India

ISBN: (纸本)9798350350593

As the application of Embedded devices in network communication increases exponentially, there is a growing necessity for effective security mechanisms that may be implemented within resource constraints. Lightweight cryptography becomes an essential solution, which includes constraints like latency, memory size, area, and power consumption. This study presents a hardware implementation of the ANU-ii and Modified ANU-ii block cipher using SPARTAN-6 Field Programmable Gate Arrays (fpgas). The design presented has a 64-bit ANU-ii and Modified ANU-ii block cipher and offers comparison analysis with alternative data path architectures according to various design parameters. The FPGA-based solution additionally be reconfigured and is flexible, thereby making it appropriate for a variety of applications that require secure data transmission. The results demonstrate that the ANU-ii and Modified ANU-ii block cipher is not only high-performing but also flexible to various system needs. This research indicates how well our suggested encryption design may address the demands of current security concerns related to data. The result of the proposed ANU-ii and Modified ANU-ii algorithm shows a maximum frequency of 313.686 MHz and 316.131 MHz and delay of 3.188 ns and 3.163 ns respectively. © 2024 IEEE.

关键词： Ciphertext

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FPGA-based Accelerator for FFT-Processing in Edge computing 12

FPGA-based Accelerator for FFT-Processing in Edge Computing

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12th IEEE International conference on Intelligent Data Acquisition and Advanced computing Systems: technology and applications, IDAACS 2023

作者： Schulz, Peter Sleahtitchi, Grigore Haw Hamburg HamburgD-20099 Germany

ISBN: (纸本)9798350358056

Edge computing bridges the gap between end devices on the Internet of Things (IoT) and central, server-based IT services by accelerating tasks which otherwise could not be executed on the IoT device itself. The Fast Fourier Transformation (FFT) is used as an example for the arithmetic tasks to be supported. To support such specific applications, we envisage a concept for edge computing in which co-processing is implemented using Field Programmable Gate Arrays (fpgas). This article first describes certain edge computing requirements using the example of moving drones. This involves the case-by-case reconfiguration of the computation hardware and a handover mechanism from one edge node to another. Then follows the description of an FPGA-based FFT accelerator unit and its extension to an FFT co-processor. The development took place under the proviso that, for example, drones can request different co-processors and that the drones can also change the edge node when changing a radio cell, which results in a handover of the co-processor context. Regarding the FPGA part this means that the co-processor is part of a partially reconfigurable environment, and the co-processor must support the handover mechanisms in terms of hardware. Finally, the need for FPGA resources is analyzed, also in comparison with alternative solutions. © 2023 IEEE.

关键词： Edge computing FFT FPGA partitial FPGA reconfiguration

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Exploiting FPGA Capabilities for Accelerated Biomedical computing 26

Exploiting FPGA Capabilities for Accelerated Biomedical Comp...

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26th IEEE Signal Processing: Algorithms, Architectures, Arrangements, and applications, SPA 2023

作者： Inadagbo, Kayode Arig, Baran Alici, Nisanur Isik, Murat Prairie View AandM University Prairie ViewTX United States Drexel University PhiladelphiaPA United States Erciyes University Kayseri Turkey

ISBN: (纸本)9798350304985

This study presents advanced neural network architectures including Convolutional Neural Networks (CNN), Recurrent Neural Networks (RNN), Long Short-Term Memory Networks (LSTMs), and Deep Belief Networks (DBNs) for enhanced ECG signal analysis using Field Programmable Gate Arrays (fpgas). We utilize the MIT-BIH Arrhythmia Database for training and validation, introducing Gaussian noise to improve algorithm robustness. The implemented models feature various layers for distinct processing and classification tasks and techniques like EarlyStopping callback and Dropout layer are used to mitigate overfitting. Our work also explores the development of a custom Tensor Compute Unit (TCU) accelerator for the PYNQ Z1 board, offering comprehensive steps for FPGA-based machine learning, including setting up the Tensil toolchain in Docker, selecting architecture, configuring PS-PL, and compiling and executing models. Performance metrics such as latency and throughput are calculated for practical insights, demonstrating the potential of fpgas in high-performance biomedical computing. The study ultimately offers a guide for optimizing neural network performance on fpgas for various applications. © 2023 Division of Signal Processing and Electronic Systems, Poznan University of technology (DSPES PUT).

关键词： Signal analysis

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