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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

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11th International Symposium on Applied reconfigurable computing, ARC 2015

11th International Symposium on Applied Reconfigurable Compu...

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11th International Symposium on Applied reconfigurable computing, ARC 2015

ISBN: (纸本)9783319162133

The proceedings contain 50 papers. The special focus in this conference is on Architecture, Modeling, Tools, applications, Network-on-a-Chip, Cryptography applications and Extended Abstracts. The topics include: Reducing storage costs of reconfiguration contexts by sharing instruction memory cache blocks;a vector caching scheme for streaming FPGA SpMV accelerators;hardware synthesis from functional embedded domain-specific languages;operand-value-based modeling of dynamic energy consumption of soft processors in FPGA;a fully parallel particle filter architecture for fpgas;Teach advanced reconfigurable architectures and tools;dynamic memory management in vivado-HLS for scalable many-accelerator architectures;place and route tools for the mitigation of single event transients on flash-based fpgas;advanced systemC tracing and analysis framework for extra-functional properties;run-time partial reconfiguration simulation framework based on dynamically loadable components;architecture virtualization for run-time hardware multithreading on field programmable gate arrays;survey on real-time network-on-chip architectures;hardware benchmarking of cryptographic algorithms using high-level synthesis tools;an efficient and flexible FPGA implementation of a face detection system;a dynamically reconfigurable mixed analog-digital filter bank;a timing driven cycle-accurate simulation for coarse-grained reconfigurable architectures;a novel concept for adaptive signal processing on reconfigurable hardware;modular acquisition and stimulation system for timestamp-driven neuroscience experiments;DRAM row activation energy optimization for stride memory access on FPGA-based systems;acceleration of data streaming classification using reconfigurable technology;partial reconfiguration for dynamic mapping of task graphs onto 2D mesh platform and a challenge of portable and high-speed FPGA accelerator.

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Large-scale high-dimensional nearest neighbor search using flash memory with in-store processing

Large-scale high-dimensional nearest neighbor search using f...

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International conference on reconfigurable computing and fpgas, ReConFig 2015

作者： Jun, Sang-Woo Chung, Chanwoo Arvind Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology United States

ISBN: (纸本)9781467394062

Modern datasets of importance such as images, videos, protein sequences or text, usually contain very high dimensional information from the search point of view. Nearest neighbor search is one of the most fundamental building blocks in dealing with large amounts of data. It is the problem of finding points in a database that are most similar to a query data point by some distance metric. There is a large body of work in algorithms for nearest-neighbor search on large highdimensional datasets. Since these algorithms invariably involve random access to data, most existing implementations ensure that the data is stored in DRAM, and does not spill into secondary storage such as hard disks. However, the immense size of modern datasets often requires hundreds of computers to accommodate the dataset in DRAM. An alternative to such a system is a much smaller cluster that stores the dataset in flash memory (instead of DRAM) and has in-store computing capability. In this paper, we build and demonstrate the performance of highdimensional nearest-neighbor search on a flash-based system with FPGA acceleration and show that it sometimes exceeds the performance of a DRAM-based solution. We chose two example applications, images and documents, for this demonstration. Since flash storage, in comparison to DRAM, is an order of magnitude cheaper and consumes an order of magnitude less power, a flashbased solution for nearest-neighbor searches offers a viable and attractive alternative. © 2015 IEEE.

关键词： Nearest neighbor search

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ILP-based modulo scheduling for high-level synthesis

ILP-based modulo scheduling for high-level synthesis

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Proceedings of the International conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES)

作者： Julian Oppermann Andreas Koch Melanie Reuter-Oppermann Oliver Sinnen Embedded Systems and Applications Group Technische Universität Darmstadt Germany Discrete Optimization and Logistics Group Karlsruhe Institute of Technology Germany Parallel and Reconfigurable Computing Group University of Auckland New Zealand

ISBN: (纸本)9781509035892

In high-level synthesis, loop pipelining is a technique to improve the throughput and utilisation of hardware datapaths by starting new loop iterations after a fixed amount of time, called the initiation interval (ii), allowing to overlap subsequent iterations. The problem is to find the smallest ii and corresponding operation schedule that fulfils all data dependencies and resource constraints, both of which are usually found by modulo scheduling. We propose Moovac1, a novel integer linear program (ILP) formulation of the modulo scheduling problem based on overlap variables to model exact resource constraints. Given enough time, Moovac will find a mimimum-ii solution. This is in contrast to Canis' state-of-the-art Modulo SDC approach, which requires heuristic simplifications of the resource constraints. Moovac can thus be used as a reference to evaluate heuristics, or in a time-limited mode as a heuristic itself to provide a best-so-far solution. We schedule kernels from the CHStone and MachSuite benchmarks for loop pipelining with Moovac, Modulo SDC and a prior exact formulation by Eichenberger. Moovac has competitive performance in its time-limited mode, and delivers better results faster than the Modulo SDC scheduler for some loops. Often its structure leads to quicker solution times than Eichenberger's formulation. Using the Moovac-computed optimal solutions as a reference, we can confirm that the Modulo SDC heuristic is indeed capable of finding optimal or near-optimal solutions for the majority of smallto medium-sized loops. However, for larger loops the two algorithms begin to diverge, with Moovac often being significantly faster to prove the infeasibility of a candidate ii. This can be exploited by running both schedulers synergistically, leading to a quicker convergence to the final ii.

关键词： Schedules Pipeline processing Hardware Clocks Digital signal processing VLIW

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A Novel Configuration Context Cache Structure of reconfigurable Systems 11

A Novel Configuration Context Cache Structure of Reconfigura...

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11th IEEE International conference on ASIC (ASICON)

作者： Gong, Yu Liu, Bo Mei, Chen Wang, Ruihe Southeast Univ Natl ASIC Syst Engn Technol Res Ctr Nanjing 210096 Jiangsu Peoples R China Southeast Univ Integrated Circuits Technol Res Inst Wuxi 214135 Peoples R China

ISBN: (纸本)9781479984855

The coarse-grained reconfigurable architecture (CGRA) is proven to be energy efficient in many domains, such as multi-media and signal processing. However, the continuous updating of configuration context limits the performance of reconfigurable systems severely. Configuration context cache is usually introduced in CGRAs to solve this problem. This paper proposes several methods to improve the performance of the configuration context cache. Firstly, the configuration context is classified into three levels. Secondly, a three-level hierarchical cache structure, based on the Pre-fetch and Hybrid-Priority strategies, is adopted to reduce the cache accessing time. Finally, a novel Two-Side-View design, including the physical view and the logic view, is implemented to reduce the cache size. The experimental results show that the proposed structure is 2.23 times and 2.06 times better than the up-to-date centralized and distributed structures. The proposed cache structure has been integrated in a reconfigurable computing processor called REMUS-ii. When processing multi-media applications, REMUS-ii can realize 1080p HiP@30fps decoding at frequency of 200MHz.

关键词： Signal processing

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Scalable Embedded Systems: Towards the Convergence of High-Performance and Embedded computing 13

Scalable Embedded Systems: Towards the Convergence of High-P...

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13th International conference on Embedded and Ubiquitous computing (EUC 2015)

作者： Giorgi, Roberto Univ Siena Siena Italy

ISBN: (纸本)9781467382991

Embedded System toolchains are highly customized for a specific System-on-Chip (SoC). When the application needs more performance, the designer is typically forced to adopt a new SoC and possibly another toolchain. The rationale for not scaling performance by using, e.g., two SoCs, is that maintining most of the operations on-chip may allow for higher energy efficiency. We are exploring the feasibility and trade-offs of designing and manufacturing a new Single Board Computer (SBC) that could serve flexibly for a number of current and future applications, by allowing scalability through clusters of SBCs while keeping the same programming model for the SBC. This board is based on fpgas and embedded processors, and its key points are: i) a fast custom interconnect for board-to-board communication and ii) an easily programmable environment which would allow both the off-loading of code into accelerators (either soft-IP blocks or hard-IP blocks) and, at the same time, the distribution of computation across boards. A key challenge to successfully deploying this paradigm is to properly distribute the threads across several boards without the explicit intervention of the programmer. In this paper we describe how to dynamically and efficiently distribute the computational threads in symbiosis with an appropriate memory model to allow the system scalability, so that we can double the performance by simply connecting two boards without i) changing the basic hardware components (e.g., to a different System-On-Chip) and ii) changing the programming model to follow the vendor specific toolchain. Our approach is to reduce data movement across boards. Our initial experiments have confirmed the feasibility of our approach.

关键词： Cyber-Physical Systems reconfigurable Systems Cluster Programming FPGA Programming Distributed Shared Memory Programming Model Performance Evaluation

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Hierarchical Library Based Power Estimator for Versatile fpgas 25

Hierarchical Library Based Power Estimator for Versatile FPG...

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25th International conference on Field Programmable Logic and applications

作者： Liang, Hao Zhang, Wei Sinha, Sharad Chen, Yi-Chung Li, Hai Hong Kong Univ Sci & technol HKUST Dept Elect & Comp Engn Kowloon Hong Kong Peoples R China Univ Pittsburgh Dept Elect & Comp Engn Pittsburgh PA USA

ISBN: (纸本)9781467381239

FPGA is a promising hardware accelerator in modern high-performance computing systems. In such a system, power is a key factor in the design requiring thermal and energy-saving considerations. Modern power estimators for FPGA either support specific hardware provided by FPGA vendors or contain power models for certain types of conventional FPGA architectures. However, with technology advancement, novel versatile FPGA architectures are introduced to further augment current FPGA architecture, such as emerging FPGA with non-volatile memory, nano-wire interconnection of reconfigurable array, etc. To evaluate the power consumption of various FPGA designs, the power estimator has to be made more flexible and extensible to support new devices and architectures. We introduce a novel power estimator with hierarchical library supporting power models at different levels, e.g. novel circuits of components, emerging memory devices, time-multiplexing architecture etc. The power estimator also supports coarse-grain or fine-grain power estimation defined by users for achieving complexity-accuracy trade-off. Simulation results of benchmarks on the proposed power estimator against commercial estimators demonstrate accuracy of our tool. The proposed tool demonstrates flexibility to estimate power for both existing FPGA architectures and new architectures.

关键词： fpga power estimator

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Efficient and flexible NoC-based group communication for secure MPSoCs

Efficient and flexible NoC-based group communication for sec...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Johanna Sepúlveda Daniel Flórez Guy Gogniat Institute for Security in Information Technology Technical University of Munich Germany Lab-STICC South Brittany University France

In order to improve the performance, embedded applications are distributed on several IP cores of Multiprocessors Systems-on-Chip (MPSoCs). Such a strategy forces the peer interaction among the different computation components, which have to exchange data through the Networkson- Chip (NoC). For applications for which security is an important concern, data exchanged among the IPs must remain confidential. Security zones are built to wrap the sensitive IPs and guarantee their protection from malicious applications. Several approaches have been proposed to create the security zones. However, due the ever-changing nature of these zones, the impact of creating and destroying the zones on the system performance is not negligible. In this work, for the first time we propose the implementation of smart security zones that efficiently create security zones by combining robust contributory group key agreement protocols and the NoC routing. Our approach can efficiently create, modify or remove continuous and disrupted security zones. We evaluate our approach under synthetic traffic patterns and the execution of SPLASH2 benchmarks. We show that our architecture is able to manage dynamic security zones while presenting low impact on the performance and cost of MPSoCs.

关键词： IP networks Firewalls (computing) Routing System performance Routing protocols

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FPGA based nodes for sub-microsecond synchronization of cyber-physical production systems on high availability ring networks

FPGA based nodes for sub-microsecond synchronization of cybe...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Armando Astarloa Naiara Moreira Unai Bidarte Marcelo Urbina David Modrono University of the Basque Country UPV/EHU Bilbao Spain Propagación Control Electrónico Networking Universidad de las Fuerzas Armadas ESPE Sangolquí Ecuador System-an-Chip engineering Bilbao Spain

Cyber-Physical Production Systems are characterized by integrating sensors, processing and communication in Industrial Environments like in advanced manufacturing plants or in the new generation Smart Grids. In these context, the accuracy on the synchronization plays a vital role because it is the base for control operations and for the correlation among the distributed sensor data sampling. In this paper the application of the IEEE1588 Synchronization protocol over High Availability Ethernet networks is applied to a new generation Cyber-Physical Production Systems in order to achieve sub-microsecond synchronization. These CPPS can be used to build rings and to interconnect rings as well. These interconnections offer bumpless Ethernet redundancy, without the need of any additional network equipment. In order to measure the resilience and the accuracy of the 1588-aware high-availability network composed by these nodes, a distributed sensors implementation composed by HSR network nodes that benefits from reconfigurable technology (small fpgas and powerful programmable SoCs)has been analyzed. As it has been verified, although in a case of network failure, the synchronization recovers automatically and the accuracy obtained is in the range of 1 μs, that offers a very good reference for many applications in the industry.

关键词： Synchronization Sensors Peer-to-peer computing Switches Logic gates Ports (Computers) IP networks

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Designing customized ISA processors using high level synthesis

Designing customized ISA processors using high level synthes...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Sam Skalicky Tejaswini Ananthanarayana Sonia Lopez Marcin Lukowiak Xilinx Inc. San Jose CA USA Rochester Institute of Technology Rochester NY USA

In this paper we propose a new degree of flexibility for soft processor design in which only the instructions relevant to the task at hand are implemented as a subset of the Instruction Set Architecture (ISA). These customized processors execute software kernels in the usual way, yet can be implemented with a fraction of the hardware resources used by other full- ISA soft processor cores. We present a design methodology for such customized ISA processors where the functional description of the processor is written in a high level language and the hardware implementation is obtained using high level synthesis (HLS) tools. We investigate the potential and limitations of the HLS tools to take processor simulator-like implementations in C/C++ and produce functional hardware processor architectures. We apply this methodology to two relevant applications -a basic linear algebra application and a cryptographic application- due to their distinct features. Our results demonstrate that these customized processors utilize significantly less hardware resources than those required by Xilinx MicroBlaze with reasonable performance degradation using HLS generated hardware exclusively.

关键词： Program processors Registers Kernel Hardware Pipeline processing Arrays

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Large-scale high-dimensional nearest neighbor search using flash memory with in-store processing

Large-scale high-dimensional nearest neighbor search using f...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Sang-Woo Jun Chanwoo Chung Arvind Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology

关键词： Nearest neighbor searches Ash Random access memory Histograms Performance evaluation Field programmable gate arrays

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