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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

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Dynamic fault recovery using partial reconfiguration for highly reliable fpgas

Dynamic fault recovery using partial reconfiguration for hig...

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Mediterranean conference on Embedded computing (MECO)

作者： Gehad I. Alkady Nahla A. El-Araby M. B. Abdelhalim H. H. Amer A. H. Madian Electronics & Comm. Eng. Dept. American University in Cairo Cairo Egypt Electrical and Electronics Eng. Dept. Canadian International College Cairo Egypt College of Computing and Information Technology AASTMT Cairo Egypt Radiation Engineering Department Egyptian Atomic Energy Authority Cairo Egypt

fpgas are becoming more popular in the domain of safety-critical applications (such as space applications) due to their high performance, re-programmability and reduced development cost. Such systems require fpgas with self-detection and self-repairing capabilities in order to cope with errors due to the harsh conditions that usually exist in such environments. In this paper, a new dynamic fault recovery technique is proposed using the runtime partial reconfiguration (PR) property in fpgas. It focuses on open interconnect faults and relies on specifying a Partially reconfigurable block in the FPGA that is only used during the recovery process after the failure of the first module in the system. The technique uses only one location to recover from errors in any of the FPGA's modules. Accordingly, it requires less area overhead when compared to other techniques.

关键词： Field programmable gate arrays Circuit faults Integrated circuit interconnections Fault tolerance Fault tolerant systems Single event upsets

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A study on detailed placement for fpgas

A study on detailed placement for FPGAs

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International conference on VLSI Systems, Architecture, technology and applications (VLSI-SATA)

作者： Sudipta Paul Rana Das Pritha Banerjee Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India Dept. of Computer Science and Engineering University of Calcutta Kolkata

Recent Field Programmable Gate Arrays (FPGA) have high logic capacity and it requires fast yet high quality placement method for mapping a technology mapped netlist of a given complex digital design onto the FPGA chip. Analytical placement for fpgas show significant scalability for large design compared to traditional simulated annealing based placement methods. However, the high quality placement achieved during global placement with overlap of logic blocks need to be legalized and fine-tuned during detailed placement efficiently in order to take advantage of the scalability of the analytical placer without compromising the quality. In this work, we study the effect of two different detailed placement methods, i) wirelength-driven, and ii) timing-driven on a legalized placement by proposing a suitable strategy specifically for fpgas. The experimental results show significant improvements of the legalized placement in terms of half-perimeter wirelength and critical path delay, emphasizing the need for better detailed placement methodologies.

关键词： Field programmable gate arrays Scalability Delays Computational modeling Analytical models Simulated annealing Area measurement

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Customizable Heterogeneous Acceleration for Tomorrow's High-Performance computing

Customizable Heterogeneous Acceleration for Tomorrow's High-...

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IEEE International Symposium on Cyberspace Safety and Security

作者： Alessandro Cilardo Jose Flich Mirko Gagliardi Rafael T. Gavila DIETI - University of Naples Federico II GAP - Universitat Politecnica de Valencia

ISBN: (纸本)9781479989386

High-performance computing as we know it today is experiencing unprecedented changes, encompassing all levels from technology to use cases. This paper explores the adoption of customizable, deeply heterogeneous manycore systems for future QoS-sensitive and power-efficient high-performance computing. At the heart of the proposed architecture is a NoC-based many-core system embracing medium-end CPUs, GPU-like processors, and reconfigurable hardware regions. The paper discusses the high-level design principles inspiring this innovative architecture as well as the key role that heterogeneous acceleration, ranging from multicore processors and GPUs down to fpgas, might play for tomorrow's high-performance computing.

关键词： High Performance computing PROCESSOR Multi-core processors acceleration

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A novel configuration context cache structure of reconfigurable systems

A novel configuration context cache structure of reconfigura...

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International conference on ASIC

作者： Yu Gong Bo Liu Chen Mei Ruihe Wang Southeast University Nanjing Jiangsu CN National ASIC System Engineering Technology Research Center Southeast University Nanjing China Integrated Circuits Technology Research Institute Southeast University Wuxi China

The coarse-grained reconfigurable architecture (CGRA) is proven to be energy efficient in many domains, such as multi-media and signal processing. However, the continuous updating of configuration context limits the performance of reconfigurable systems severely. Configuration context cache is usually introduced in CGRAs to solve this problem. This paper proposes several methods to improve the performance of the configuration context cache. Firstly, the configuration context is classified into three levels. Secondly, a three-level hierarchical cache structure, based on the Pre-fetch and Hybrid-Priority strategies, is adopted to reduce the cache accessing time. Finally, a novel Two-Side-View design, including the physical view and the logic view, is implemented to reduce the cache size. The experimental results show that the proposed structure is 2.23 times and 2.06 times better than the up-to-date centralized and distributed structures. The proposed cache structure has been integrated in a reconfigurable computing processor called REMUS-ii. When processing multi-media applications, REMUS-ii can realize 1080p HiP@30fps decoding at frequency of 200MHz.

关键词： Context Indexes Table lookup Decoding Kernel Continuous wavelet transforms Signal processing algorithms

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An Architectural Approach for reconfigurable Industrial I/O Devices

An Architectural Approach for Reconfigurable Industrial I/O ...

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2014 International conference on reconfigurable computing and FAGAs

作者： Kirschberger, Daniel Flatt, Holger Jasperneite, Juergen Fraunhofer IOSB INA Applicat Ctr Ind Automat Langenbruch 6 D-32657 Lemgo Germany

ISBN: (纸本)9781479959440

This paper presents an architecture concept for reconfigurable industrial I/O devices. In order to avoid the use of special hardware modules as well as to offload the PLC from real-time preprocessing of sensor data, these tasks are shifted into the reconfigurable I/O device. Therefore, an FPGA based architecture template is proposed that supports loading of application-specific functions into the I/O device at runtime. The architecture template is partitioned into a static part and several reconfigurable slots. While the static part implements all fixed design elements, like the communication with the field bus and the in-system CPU, all application-specific functions are mapped onto the reconfigurable slots. In order to perform the reconfiguration of application-specific functions at runtime, the partial reconfiguration technology of modern fpgas is used. The proposed concept is evaluated by mapping a case study with four reconfigurable slots onto a Xilinx Zynq-7000 SoC. The results show that new application-specific functions can be flexibly loaded into the I/O device. The total reconfiguration process of exemplary application-specific functions requires up to 3 ms and cause down-times below 0.5 ms. This especially enables new control applications that can even change the preprocessing within I/O devices during cyclic data communication.

关键词： field programmable gate arrays reconfigurable architectures system-on-chip FPGA based architecture template Xilinx Zynq-7000 SoC architectural concept reconfigurable industrial I/O device static part Automation Computer architecture Control systems Field programmable gate arrays Hardware Performance evaluation Runtime environment Field programmable gate arrays IO reconfigurable architectures Computer Architecture system-on-chip control systems configurability Computer hardware Automation Performance Evaluation Operating Environment Reconfiguration

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Hierarchical library based power estimator for versatile fpgas

Hierarchical library based power estimator for versatile FPG...

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International conference on Field Programmable Logic and applications

作者： Hao Liang Wei Zhang Sharad Sinha Yi-Chung Chen Hai Li Department of Electronic and Computer Engineering The Hong Kong University of Science and technology (HKUST) Clear Water Bay Kowloon Hong Kong Department of Electrical and Computer Engineering University of Pittsburgh Pittsburgh Pennsylvania USA

FPGA is a promising hardware accelerator in modern high-performance computing systems. In such a system, power is a key factor in the design requiring thermal and energy-saving considerations. Modern power estimators for FPGA either support specific hardware provided by FPGA vendors or contain power models for certain types of conventional FPGA architectures. However, with technology advancement, novel versatile FPGA architectures are introduced to further augment current FPGA architecture, such as emerging FPGA with non-volatile memory, nano-wire interconnection of reconfigurable array, etc. To evaluate the power consumption of various FPGA designs, the power estimator has to be made more flexible and extensible to support new devices and architectures. We introduce a novel power estimator with hierarchical library supporting power models at different levels, e.g. novel circuits of components, emerging memory devices, time-multiplexing architecture etc. The power estimator also supports coarse-grain or fine-grain power estimation defined by users for achieving complexity-accuracy trade-off. Simulation results of benchmarks on the proposed power estimator against commercial estimators demonstrate accuracy of our tool. The proposed tool demonstrates flexibility to estimate power for both existing FPGA architectures and new architectures.

关键词： Field programmable gate arrays Estimation Libraries Power demand Routing Table lookup

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Towards dark silicon era in fpgas using complementary hard logic design 24

Towards dark silicon era in FPGAs using complementary hard l...

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24th International conference on Field Programmable Logic and applications, FPL 2014

作者： Ahari, Ali Khaleghi, Behnam Ebrahimi, Zahra Asadi, Hossein Tahoori, Mehdi B. Department of Computer Engineering Sharif University of Technology Tehran Iran Dependable Nano Computing Karlsruhe Institute of Technology Karlsruhe Germany

ISBN: (纸本)9783000446450

While the transistor density continues to grow exponentially in Field-Programmable Gate Arrays (fpgas), the increased leakage current of CMOS transistors act as a power wall for the aggressive integration of transistors in a single die. One recently trend to alleviate the power wall in fpgas is to turn off inactive regions of the silicon die, referred to as dark silicon. This paper presents a reconfigurable architecture to enable effective fine-grained power gating of unused Logic Blocks (LBs) in fpgas. In the proposed architecture, the traditional soft logic is replaced with Mega Cells (MCs), each consists of a set of complementary Generic reconfigurable Hard Logic (GRHL) and a conventional Look-Up Table (LUT). Both GRHL cells and LUTs can be power gated and turned off by controlling configuration bits. In the proposed MC, only one cell is active and the others are turned off. Experimental results on MCNC benchmark suite reveal that the proposed architecture reduces the critical path delay, power, and Power Delay Product (PDP) of LBs up to 5.3%, 30.4%, and 28.8% as compared to the equivalent LUT-based architecture. © 2014 Technical University of Munich (TUM).

关键词： reconfigurable architectures

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Design and evaluation of N-module reconfigurable systems

Design and evaluation of N-module reconfigurable systems

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International conference on Advanced computing, Networking and Informatics, ICACNI 2013

作者： Parikh, Kunal Yogeshkumar Manikandan, J. Agrawal, V.K. Crucible of Research and Innovation PES Institute of Technology 100-ft Ring Road BSK 3rd Stage BangaloreKarnataka560085 India

ISBN: (纸本)9788132216643

reconfigurable system is defined as the ability of a single system to get reconfigured to perform multiple applications. reconfigurable systems are intended to reduce the hardware resources required for a system, power dissipation, and overall cost of the system. Static random access memory (SRAM)-based fieldprogrammable gate arrays (fpgas) are the best choice for designing reconfigurable systems. In this paper, different approaches of designing a reconfigurable system on Virtex-5 FPGA are discussed. In order to assess the significance of reconfigurable systems, three sets of N-module reconfigurable system are proposed and their performance results are reported in this paper. © Springer India 2014.

关键词： Field programmable gate arrays (FPGA)

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The design methodology of a High-Performance dataflow supercomputer on a reconfigurable chipset for use in 3D graphics applications 12

The design methodology of a High-Performance dataflow superc...

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2014 12th IEEE International conference on Solid-State and Integrated Circuit technology, ICSICT 2014

作者： Li, Yongsheng Chen, Stanley L. Zhang, Wenhao Li, Xiaojun Tao, Xu Zhang, Limin Yuan, Shiming Chu, Jingfeng School of Software and Microelectronics Peking University Wuxi214125 China Variel Microelectronics Corporation Nanjing210046 China

ISBN: (纸本)9781479932962

The dataflow supercomputer outperforms the conventional multi-core supercomputers based on CPU/ GPUs in compute-intensive exascale High Performance computing (HPC) applications by orders of magnitude in terms of computing and power performance [1]. The best performance has been reported by application-specific heterogeneous dataflow supercomputers built on commercial fpgas with a speedup over 200× compared to a single-core computer [2]. As an HPC application, a 3D graphics application for massively complex models is in an urgent need of high-performance computing and low power consumption. In this paper, an innovative chipset-on-card design methodology for 3D supercomputing applications based on K-dimensional binary space partitioning (BSP) out-of-core ray-tracing algorithm [3] is described for achieving a performance higher than the reported dataflow supercomputers. This algorithm is reformulated as a set of parallel pipelines with minimal data exchange and partitioned into separate data flows. The entire data flow diagram is then mapped into a reconfigurable high-performance computing chipset-on-card. © 2014 IEEE.

关键词： Supercomputers

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A Power Efficient reconfigurable System-in-Stack: 3D Integration of Accelerators, fpgas, and DRAM 27

A Power Efficient Reconfigurable System-in-Stack: 3D Integra...

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27th IEEE International System-on-Chip conference (IEEE SOCC)

作者： Gadfort, Peter Dasu, Aravind Akoglu, Ali Leow, Yoon Kah Fritze, Michael Univ Southern Calif Inst Informat Sci Arlington VA 22203 USA Univ Arizona Dept Elect & Comp Engn Tucson AZ USA

ISBN: (纸本)9781479933785

Increasing computing power efficiency has become more important as more applications are moving to mobile platforms, which tend to have a limited power available. Being able to perform a wide variety of computations efficiently is especially important for power constrained embedded applications such as unmanned aerial vehicles (UAVs), which may not be able to send the data out for processing and must perform some of the processing on-board. This paper describes a 3D FPGA-DRAM architecture that can not only deliver the necessary flexibility, by using fpgas, but also provide the computing efficiency in the form of floating-point arithmetic accelerators that is required for UAVs. We examine the efficiency of this system in 65 nm, 90 nm, and 130 nm CMOS technologies and report simulation results showing a peak computing efficiency of 28.94 GFLOPs/W for a 4,096 point 1 dimensional FFT and 25.03 GFLOPs/W for a 1,024 point x 1,024 point 2 dimensional FFT.

关键词： Benchmark testing Computer architecture Field programmable gate arrays Random access memory Switches Three-dimensional displays Video recording Field programmable gate arrays three-dimensional displays Benchmark testing random access machine Video Recording Computer Architecture Switches DRAM1 gene Unmanned Aerial Vehicle Accelerators available power moving platform CMOS technology embedded application

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