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An Efficient Implementation of PBKDF2 with RIPEMD-160 on Multiple fpgas 20

An Efficient Implementation of PBKDF2 with RIPEMD-160 on Mul...

引用

20th IEEE International conference on Parallel and Distributed Systems (ICPADS)

作者： Abbas, Ayman Voss, Rian Wienbrandt, Lars Schimmler, Manfred Christian Albrechts Univ Kiel Dept Comp Sci D-24098 Kiel Germany

ISBN: (纸本)9781479976157

A weakness of many security systems is the strength of the chosen password or key derivation function. We show how FPGA technology can be used to effectively attack cryptographic applications with a password dictionary. We have implemented two independent PBKDF2 cores each using four HMAC cores with pipelines calculating a RIPEMD-160 hash to derive encryption keys together with one resource optimized AES-256 XTS core for direct decryption on a Xilinx Spartan6-LX150 FPGA. Our design targets TRUECRYPT containers, but may be applied to similar encryption tools with little adaption. In order to save resources and maximize speed, we have further optimized the RIPEMD-160 hash function for this purpose. Our design executed on the multi-FPGA system RIVYERA S6-LX150 containing 128 S6-LX150 fpgas, finally reaches a peak performance of about 245,000 passwords per second.

关键词： known-plaintext dictionary attack AES-XTS RIPEMD-160 PBKDF2 FPGA reconfigurable high-performance computing

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A hybrid hierarchical topology and mapping approach oriented to HPCs

A hybrid hierarchical topology and mapping approach oriented...

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2014 International conference on Communication technology and Application, CTA 2014

作者： Xiao, C.H. Huang, Z.Q. Li, D. Embedded Software and System Institution Beijing University of Technology Beijing China

ISBN: (纸本)9781845649302

To target the problems of performance, cost and energy consumption in large scale communications of high performance computing, a hybrid hierarchical topology and corresponding partitioning approach are proposed in this paper. The proposed hierarchical topology taking full advantages of both traditional metallic lines and emerging interconnections to implement one-hop local direct communication within the cluster and one-hop global high-speed communication between clusters. The customized interconnection topology can be designed according different applications through the proposed partitioning approach to get a better trade-off between performance and cost. The case study proved that the partitioning approach can implement the fast mapping from the design to real high performance computing system with multi-fpgas, and accelerate the realization of high performance reconfigurable computing systems. © 2014 WIT Press.

关键词： Field programmable gate arrays (FPGA)

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Human Aware Superorganisms

Human Aware Superorganisms

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ACM International Joint conference on Pervasive and Ubiquitous computing (UbiComp)

作者： Bicocchi, Nicola Fontana, Damiano Zambonelli, Franco Univ Modena & Reggio Emilia Dipartimento Ingn Enzo Ferrari Modena Italy Univ Modena & Reggio Emilia Dipartimento Sci & Metodi Ingn Modena Italy

ISBN: (纸本)9781450330473

Massive networks of wearable devices have recently become a key scenario for pattern recognition technologies. applications range from implicit human-machine interactions, to autonomous monitoring of user habits and activities. This paper presents a framework providing developers with tools to orchestrate the continuous process of collecting and classifying data streams in aware-systems. It supports service oriented, reconfigurable components and provides a solid background to put at joint work specification- and data-driven approaches. It also provides an innovative meta-classification scheme allowing to implement applications by editing a simple state automata. Experimental results suggest that the approach could be integrated in a number of applications for: (i) improving energy efficiency, (ii) improving classification accuracy and (iii) improving software engineering of aware systems.

关键词： Wearable technology

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Enabling FPGA support in Matlab based heterogeneous systems

Enabling FPGA support in Matlab based heterogeneous systems

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： Sam Skalicky Tyler Kwolek Sonia Lopez Marcin Lukowiak Rochester Institute of Technology Rochester NY USA

fpgas have been shown to provide orders of magnitude improvement over CPUs and GPUs in terms of absolute performance and energy efficiency for various kernels such as Cholesky decomposition, matrix inversion, and FFT among others. Despite this, the overall performance of many applications suffer when implemented entirely in fpgas. Combining fpgas with CPUs and GPUs provides the range of capabilities needed to support diverse computational requirements of applications. Integrating fpgas into these systems challenges application developers with constructing hardware kernel implementations and interfacing from the low level hardware logic in the FPGA to the high speed networks that connect processors in the system. In this work we extend the compute capabilities of Matlab by incorporating support for fpgas and automating the parallel code generation. We characterize the system and evaluate the performance gains that can be achieved by adding the FPGA for two compute intensive applications. We present performance results for medical imaging and fluid dynamics applications implemented in a CPU+GPU+FPGA system and achieved up to 40× improvement compared to the standard Matlab CPU+GPU environment.

关键词： Field programmable gate arrays Graphics processing units Kernel MATLAB Instruction sets Hardware

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An adaptive victim cache scheme

An adaptive victim cache scheme

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Osvaldo Navarro Michael Hübner Department of Electrical Engineering and Information Technology Ruhr-Universität Bochum Bochum Germany

A victim cache is a small cache block usually located between two main cache levels, which main objective is to recover conflict cache misses. In the usual case, the victim cache is designed as an always enabled cache block with fixed size. However, different applications may have very different memory access requirements. In this article, we present an analysis of the relations between a victim cache, the cache's logical organization and the application's behaviour, and based on preliminary results, an victim cache scheme which is reconfigured at runtime to adapt to the current conditions of the system is proposed.

关键词： Runtime Organizations Energy consumption Mathematical model Computer architecture Benchmark testing Equations

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A systematic study of lightweight hash functions on fpgas

A systematic study of lightweight hash functions on FPGAs

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Bernhard Jungk Leandro Rodrigues Lima Matthias Hiller easycore GmbH Erlangen Germany Design Informatik Medien RheinMain University of Applied Sciences Wiesbaden Germany Institute for Security in Information Technology Technische Universitat Munchen Munich Germany

Lightweight cryptography provides cryptographic algorithms for resource constrained devices and typically aims for low-cost ASIC applications like RFID tags. In addition, it also provides attractive performance - security trade-offs for fpgas in scenarios with strict area constraints. This work presents FPGA implementations of the popular lightweight hash functions KECCAK-200 and KECCAK-400, PHOTON and SPONGENT, and gives a systematic analysis of size and throughput. The ratio between throughput and slices is a relative performance measure that enables a fair comparison among different algorithms and implementation strategies. The comparison shows that the size of the presented implementations differs over roughly one order of magnitude and the throughput over more than one order of magnitude. The SPONGENT implementation provided the highest throughput per area ratios.

关键词： Photonics Throughput Field programmable gate arrays Random access memory Cryptography Clocks

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An architectural approach for reconfigurable industrial I/O devices

An architectural approach for reconfigurable industrial I/O ...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Daniel Kirschberger Holger Flatt Jürgen Jasperneite Fraunhofer IOSB-INA Application Center Industrial Automation Lemgo Germany

This paper presents an architecture concept for reconfigurable industrial I/O devices. In order to avoid the use of special hardware modules as well as to offload the PLC from real-time preprocessing of sensor data, these tasks are shifted into the reconfigurable I/O device. Therefore, an FPGA based architecture template is proposed that supports loading of application-specific functions into the I/O device at runtime. The architecture template is partitioned into a static part and several reconfigurable slots. While the static part implements all fixed design elements, like the communication with the field bus and the in-system CPU, all application-specific functions are mapped onto the reconfigurable slots. In order to perform the reconfiguration of application-specific functions at runtime, the partial reconfiguration technology of modern fpgas is used. The proposed concept is evaluated by mapping a case study with four reconfigurable slots onto a Xilinx Zynq-7000 SoC. The results show that new application-specific functions can be flexibly loaded into the I/O device. The total reconfiguration process of exemplary application-specific functions requires up to 3 ms and cause down-times below 0.5 ms. This especially enables new control applications that can even change the preprocessing within I/O devices during cyclic data communication.

关键词： Field programmable gate arrays Performance evaluation Hardware Automation Computer architecture Runtime environment Control systems

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Hardware Task-Status Manager for an RTOS with FIFO communication

Hardware Task-Status Manager for an RTOS with FIFO communica...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Pavel G. Zaykov Georgi Kuzmanov Anca Molnos Kees Goossens Delft University of Technology CE Lab. Delft CD The Netherlands CEA LETI Grenoble France ES group Eindhoven University of Technology AZ Eindhoven The Netherlands

In this paper, we address the problem of improving the performance of real-time embedded Multiprocessor System-on-Chip (MPSoC). Such MPSoCs often execute data-flow applications composed of multiple tasks, which communicate through First-In-First-Out (FIFO) queues. The tasks on each processor in the MPSoC are scheduled for execution by an instance of a Real-Time Operating System (RTOS). To improve performance, we propose a Hardware Task-Status Manager (HWTSM) block that reduces the Worst Case Execution Time (WCET) of the RTOS. The HWTSM is a Molen-style Custom computing Unit (CCU), a coprocessor that determines the execution eligibility of tasks from FIFO-filling information. Furthermore, we propose a new processor-coprocessor execution model, denoted as parallel non-blocking. In this model the HWTSM execution overlaps with the execution of RTOS and user applications. The HWTSM is integrated into the existing CompSoC platform and this entire system is prototyped on a Xilinx XC5VFX130T FPGA chip. We experiment with two types of applications running in software, i.e., synthetic and real. With the synthetic applications, the results indicate a WCET reduction of the RTOS between 1.1 and 3.0 times. For each one of the real applications - JPEG and H.264 decoders, the experimental results indicate a WCET reduction of the RTOS by 1.3 and 1.6 times, respectively. The overall system performance gain vary from from 0.9% to 13.3% for synthetic applications, from 2.3% to 4.6% for the JPEG decoder, and from 3.8% to 7.5% for the H.264 decoder.

关键词： Hardware Coprocessors Software Computational modeling Acceleration Processor scheduling Real-time systems

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An AXI compatible cypress EZ-USB FX3 interface for USB-3.0 SuperSpeed

An AXI compatible cypress EZ-USB FX3 interface for USB-3.0 S...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Benedikt Janßen Michael Hübner Timo Jaeschke Ruhr-Universitat Bochum Bochum Nordrhein-Westfalen DE Embedded Systems for Information Technology Ruhr-University Bochum Bochum Germany Integrated Systems Ruhr-University Bochum Bochum Germany

In this paper, we introduce an IP-core which operates as glue logic between the programmable logic of a FPGA and a Cypress EZ-USB FX3 (FX3) USB-3.0 transceiver. The developed IP core communicates with other logic via AXI-4 and enables half duplex connections between the linked logic and the FX3. Thereby the platform can be used by several applications which need a high speed communication to a USB-3.0 capable host. We chose an Enclustra Mercury KX1 board for implementation, which provides the FX3 USB-3.0 transceiver chip, a Xilinx Kintex-7 FPGA and 1 GB of DDR3 SDRAM. As an application we present a radar system. The stream of radar data is received inside the Kintex-7 by a Xilinx JESD204 IP-core and buffered in the DDR3 SDRAM. For processing, the buffered data is transmitted to a host computer via the introduced IP-core. This paper shows our implementation approach, achieved transmission rates, as well as other IP-core features and gives an outlook on future advancements and applications.

关键词： Field programmable gate arrays Radar imaging Computers Data transfer Computer architecture

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A Cluster-based Hierarchical Partitioning Approach for Multiple fpgas

A Cluster-based Hierarchical Partitioning Approach for Multi...

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The 6th International conference on Computer Research and Development

作者： Chunhua Xiao Zhangqin Huang Da Li Beijing University of Technology Embedded Software and System Institution

Most high performance computing systems are large-scale computing systems, and consist tens of thousands computing nodes with superior capabilities. fpgas are able to accelerate large scope and complicated computing with flexible configurations. More and more companies and research institutions integrate multi-fpgas into high performance computing systems to get a better trade-off between high-performance and low power. How to design an effective topology for these integrated multi-fpgas according different applications has become a key problem in this area. Acluster based architectureand corresponding partitioning approach are proposed in this paper. The proposed hierarchical topology taking full advantages of both traditional metallic lines and emerging interconnections to implement one-hop local communication within the cluster and one-hop global high-speed communication between clusters. The case study proved that the proposed architecture and partitioning approach can implement the fast mapping from the design to real computing system with multi-fpgas, and accelerate the realization of high performance reconfigurable computing systems.

关键词： High performance computing multi-FPGA architecture FPGA partitioning emerging interconnections

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