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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

共 418 条记录，以下是121-130 订阅

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The design methodology of a High-Performance dataflow supercomputer on a reconfigurable chipset for use in 3D graphics applications

The design methodology of a High-Performance dataflow superc...

引用

International conference on Solid-State and Integrated Circuit technology

作者： Li Yongsheng Stanley L. Chen Zhang Wenhao Li Xiaojun Xu Tao Zhang Limin Yuan Shiming Chu Jingfeng School of Software and Microelectronics Peking University Wuxi CHINA Variel Microelectronics Corporation Nanjing CHINA

ISBN: (纸本)9781479932849

The dataflow supercomputer outperforms the conventional multi-core supercomputers based on CPU/ GPUs in compute-intensive exascale High Performance computing (HPC) applications by orders of magnitude in terms of computing and power performance [1]. The best performance has been reported by application-specific heterogeneous dataflow supercomputers built on commercial fpgas with a speedup over 200× compared to a single-core computer [2]. As an HPC application, a 3D graphics application for massively complex models is in an urgent need of high-performance computing and low power consumption. In this paper, an innovative chipset-on-card design methodology for 3D supercomputing applications based on K-dimensional binary space partitioning (BSP) out-of-core ray-tracing algorithm [3] is described for achieving a performance higher than the reported dataflow supercomputers. This algorithm is reformulated as a set of parallel pipelines with minimal data exchange and partitioned into separate data flows. The entire data flow diagram is then mapped into a reconfigurable high-performance computing chipset-on-card.

关键词： Three-dimensional displays Acceleration Supercomputers Abstracts Hardware design languages Graphics Ports (Computers)

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A hybrid hierarchical topology and mapping approach oriented to HPCs

A hybrid hierarchical topology and mapping approach oriented...

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2014 International conference on Communication technology and Application(CTA2014)

作者： C.H.Xiao Z.Q.Huang D.Li Embedded Software and System Institution Beijing University of Technology

ISBN: (纸本)9781845649302

To target the problems of performance, cost and energy consumption in large scale communications of high performance computing, a hybrid hierarchical topology and corresponding partitioning approach are proposed in this paper. The proposed hierarchical topology taking full advantages of both traditional metallic lines and emerging interconnections to implement one-hop local direct communication within the cluster and one-hop global high-speed communication between clusters. The customized interconnection topology can be designed according different applications through the proposed partitioning approach to get a better trade-off between performance and cost. The case study proved that the partitioning approach can implement the fast mapping from the design to real high performance computing system with multi-fpgas, and accelerate the realization of high performance reconfigurable computing systems.

关键词： high performance computing multi-FPGA architecture FPGA portioning emerging interconnections

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Extracting Memory-Level Parallelism through reconfigurable Hardware Traces

Extracting Memory-Level Parallelism through Reconfigurable H...

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： Lin, Mingjie Cheng, Shaoyi Wawrzynek, John

ISBN: (纸本)9781479920785

This paper proposes a new FPGA-based embedded computer architecture, which focuses on how to construct an application-specific memory access network capable of extracting the maximum amount of memory-level parallelism on a per-application basis. Specifically, through performing dynamic memory analysis and utilizing the capabilities of modern FPGA devices: abundant distributed block RAMs and programmability, the proposed reconfigurable architecture synthesizes highly efficient accelerators that enable parallelized memory accesses, and therefore accomplish effective data orchestration by maximally extracting the target application's instruction, loop and memory-level parallelism. To validate our proposed architecture, we implemented a baseline embedded processor platform, a conventional CPU+accelerator with a centralized single memory, and a prototype based on Xilinx MicroBlaze technology. Our experimental results have shown that on average for 5 benchmark applications from SPEC2006 and MiBench [1], our proposed architecture achieves 8.6 times speedup compared to the baseline embedded processor platform and 1.7 times speedup compared to a conventional CPU+accelerator platform. More interestingly, the proposed platform achieves more than 40% reduction in energy-delay product compared to a conventional CPU+accelerator with a centralized memory.

关键词： reconfigurable architectures

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Secure remote updating of bitstream in partial reconfigurable embedded systems based on FPGA

Secure remote updating of bitstream in partial reconfigurabl...

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2013 International conference on computing, Management and Telecommunications, ComManTel 2013

作者： Thanh, Tran Tiep, Vu Huu Vu, Tran Hoang Nam, Pham Ngoc Van Cuong, Nguyen School of Electronics and Telecommunications Ha Noi University of Science and Technology Ha Noi Viet Nam Faculty of Electronics and Telecommunications Da Nang University of Technology Da Nang Viet Nam

ISBN: (纸本)9781467320870

Intellectual Property protection on fpgas is a major challenge for FPGA manufacturers. Adding security features to the FPGA is not difficult but there is no consistency among the different manufacturers. Meanwhile, more features will increase resource costs and product prices, forcing users to pay for all these features even if they do not use them. As a result, decoders are often not integrated inside low-cost fpgas. To protect an FPGA-based system of this kind, we must build separate security solutions. This paper presents the importance of bit stream security, including a number of attack scenarios and FPGA bitstream security methods. We introduced bitstream encryption and authentication solutions in partial reconfigurable embedded systems based on the MicroBlaze soft-core processor aimed at improving the flexibility of the system. The highlight of our solution is that it can be applied to systems that use embedded processor. This is most practical when using shared resources (soft-core processors, memory...) for different target applications. © 2013 IEEE.

关键词： Field programmable gate arrays (FPGA)

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An Open-Source SATA Core for Virtex-4 fpgas

An Open-Source SATA Core for Virtex-4 FPGAs

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12th International conference on Field-Programmable technology (FPT)

作者： Gorman, Cory Siqueira, Paul Tessier, Russell Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA

ISBN: (纸本)9781479921980;9781479921997

In this demonstration, we present an open-source Serial ATA core designed for Virtex-4 fpgas. This core utilizes the RocketIO Multi-Gigabit Transceiver (MGT) of the Virtex-4 to interface with hard drives at SATA Generation 1 (SATA I, 1.5 Gb/s) and Generation 2 (SATA ii, 3.0 Gb/s) speeds. A full design hierarchy from host software to the physical layer is provided with the distribution to facilitate design use. A simple, FIFO interface allows for easy integration with other FPGA modules. The demonstration illustrates the correct write and read behavior of the core using a Xilinx ML405 board and a solid state disk. The peak transfer rate of the core for SATA I (130 MB/s) is demonstrated. Our goal for the demonstration is to educate the reconfigurable computing community regarding the availability of the core and to illustrate its capabilities.

关键词： serial ATA core Hard drives combination rate open source Physical layer

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RAW: A novel reconfigurable architecture design using wireless for future generation supercomputers 1

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4th International conference on Networks and Communications, NetCom 2012

作者： Viginesh, S. Vijayraghavan, G. Srinath, S. Anna University Chennai Tamil Nadu India

ISBN: (数字)9781461461548

ISBN: (纸本)9781461461531

Current day Grand Challenge applications have conscripted scientists to move towards developing high performance computers. These applications are a part of varied scientific and engineering domains whose solution is impossible without the exercise of high performance computers. The need for faster computing in the order of exaFLOPs requires a type of architecture which complies with the power to performance ratio, satisfying the requirements of the end user. In this paper we present you a design for a node as well as cluster architecture of a high performance cum power aware supercomputer. The node architecture of the proposed design paradigm is made to be more application specific by the application of fpgas or ASICs catering to the need of Grand Challenge applications. A wireless routing technology is used for higher level communication i.e. inter application communication. Wireless technology makes architecture more reconfigurable catering to the communication complexity of different algorithms in the grand challenge applications. More over using wireless technology for higher level communication reduces the power consumption to a large extent thereby making this design paradigm suitable for varied class of grand challenge applications. © 2013 Springer Science+Business Media.

关键词： Supercomputers

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ModHDL: A modular and expandable language for developing synchronous hardware

ModHDL: A modular and expandable language for developing syn...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Fabian May Friedrich Mayer-Lindenberg Institute of Computer Technology Hamburg University of Technology Hamburg Germany

With each product generation the number of application domains fpgas are suitable for is increasing. However, the rising complexity of devices and applications induce the need for more abstract and efficient programming languages. Many research projects have already addressed the improvement of hardware description languages (HDLs). Since each resulting work is tied to its own framework, an extension or combination of such to adopt for a specific application is hardly possible. In this work an expandable and modular HDL (modHDL) is presented which has been developed by applying the Language Oriented Programming paradigm. modHDL consists of a set of modular languages, each with its own scope but with a generic interface to combine or extend for specific requirements. We will discuss the base language with three extension languages covering their own application domain. Furthermore, the utilization process of these languages for further extensions is analyzed in order to demonstrate the convenience of modHDL for high-level hardware design.

关键词： Hardware DSL Semantics Field programmable gate arrays Integrated circuit modeling Abstracts Generators

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A restricted dynamically reconfigurable architecture for low power processors

A restricted dynamically reconfigurable architecture for low...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Takeshi Hirao Dahoo Kim Itaru Hida Tetsuya Asai Masato Motomura Hokkaido University Graduate School of Information Science and Technology Sapporo Hokkaido Japan

reconfigurable processors have widely attracted attention as an approach to realize high-performance and highly energy-efficient processors that map a target program's hot path to a reconfigurable datapath. In this paper, we propose a Control-Flow Driven Data-Flow Switching (CDDS) variable datapath architecture for embedded applications that demand extremely low power consumption in a wide range of uses. This architecture is characterized by following two features: (1) achieving both flexibility and low energy consumption by limiting the scope of the dynamic reconfiguration, (2) realizing smooth migration from the existing architecture by mapping the existing instruction sequence to the datapath. Preliminary evaluation on small programs have revealed that the CDDS accelerator achieves approximately 3 to 6 times the performance/power improvements, compared to a base processor.

关键词： Program processors Context Arrays Registers Hardware Switches

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A fault attack on a hardware-based implementation of the secure hash algorithm SHA-512

A fault attack on a hardware-based implementation of the sec...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Abdulhadi Shoufan Khalifa University of Science Technology and Research Abu-Dhabi UAE

Cryptographic hash functions are frequently used as basic components in cryptographic schemes such as message authentication codes, one-time signature schemes, and random number generators. In such applications the input to the hash function is a secret key or secret data. An investigation of the hash function against implementation attacks in such cases is indispensable. This paper presents a fault attack on the secure hash algorithm using the example of SHA-512. A fault model is proposed that relies on flipping two control bits to reduce the round number of the SHA-512 algorithm. By means of this attack the first data block can be extracted completely. The attack was applied to a keyed-hash message authentication code to reveal its secret key. A countermeasure is proposed to detect and prevent the attack. The attack and the countermeasure were evaluated for an FPGA implementation.

关键词： Cryptography Hardware Circuit faults Registers Trojan horses Tablet computers Message authentication

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Processor arrays generation for matrix algorithms used in embedded platforms

Processor arrays generation for matrix algorithms used in em...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Roberto Perez-Andrade Cesar Torres-Huitzil Rene Cumplido Juan M. Campos Advanced Studies Center of the National Polytechic Institute Information Technology Laboratory Ciudad Victoria Mexico Department of Computer Science National Institute for Astrophysics Optics and Electronics Puebla Mexico

Matrix algorithms are an important part of many digital signal processing applications as they are core kernels that usually need to be applied many times. Hardware assisted implementations using fpgas provide a good compromise between performance, cost and power consumption. This paper presents a high level synthesis approach to generate embedded processor arrays for matrix algorithms based on the polytope model. The proposed approach provides a solution for efficient data memory accesses and data transferring for feeding the processor array, as well as it provides support for solving a set of problem size depending on FPGA available resources. The proposed approach has been validated by generating processor arrays for two case studies targeted for a Spartan-6 device. Results show that the implemented array outperforms hardware and software implementations targeted to embedded platforms as well.

关键词： Parallel processing Arrays Array signal processing Process control Indexes Generators Clocks

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