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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

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Extracting memory-level parallelism through reconfigurable hardware traces

Extracting memory-level parallelism through reconfigurable h...

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： Mingjie Lin Shaoyi Cheng John Wawrzynek Institute of Computing Technology Chinese Academy of Sciences Beijing China Dept. of Computer and Information Science Ohio State University Columbus OH USA

This paper proposes a new FPGA-based embedded computer architecture, which focuses on how to construct an application-specific memory access network capable of extracting the maximum amount of memory-level parallelism on a per-application basis. Specifically, through performing dynamic memory analysis and utilizing the capabilities of modern FPGA devices: abundant distributed block RAMs and programmability, the proposed reconfigurable architecture synthesizes highly efficient accelerators that enable parallelized memory accesses, and therefore accomplish effective data orchestration by maximally extracting the target application's instruction, loop and memory-level parallelism. To validate our proposed architecture, we implemented a baseline embedded processor platform, a conventional CPU +accelerator with a centralized single memory, and a prototype based on Xilinx MicroBlaze technology. Our experimental results have shown that on average for 5 benchmark applications from SPEC2006 and MiBench [1], our proposed architecture achieves 8.6 times speedup compared to the baseline embedded processor platform and 1.7 times speedup compared to a conventional CPU+accelcrator platform. More interestingly, the proposed platform achieves more than 40% reduction in energy-delay product compared to a conventional CPU+accelerator with a centralized memory.

关键词： Hardware Parallel processing Computer architecture Acceleration Performance evaluation Field programmable gate arrays Coherence

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A reconfigurable architecture for searching optimal software code to implement block cipher permutation matrices

A reconfigurable architecture for searching optimal software...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Elif Bilge Kavun Gregor Leander Tolga Yalcind Horst Görtz Institute for IT-Security Ruhr-Universität Bochum Germany University for Information Science and Technology “St. Paul the Apostle “ Ohrid Macedonia

Programming in embedded systems has always been a challenge. Highly-constrained nature of embedded devices invalidates conventional coding practices. The whole practice turns into a skill game that heavily depends on the personal skills and experience of the programmer. Embedded security applications are no exceptions. Efficient software implementation of symmetric cryptography primitives such as substitution or permutation layers is a hard task and no systematic approach exists. In this study, we propose an efficient reconfigurable hardware architecture to find the most optimal code for the realization of block cipher permutation layers on embedded microcontrollers. The proposed architecture is highly parallel and realized on two Xilinx Virtex-6 XC6VLX240T fpgas. It operates on a limited set of instructions pertinent to implementation of linear matrices. Predetermined number of instructions is executed in a pipelined manner and the resultant output register contents are checked either for match to a target matrix or for certain cryptographic properties. The realized architecture uses instructions from 8-bit AVR instruction set. However, it can easily be modified to work with instruction sets of different processors. Using our parallel architecture, we have been able to find several good permutation layer matrices with branch number 4 that can be realized with only 8 instructions. We were able to search up to 11 instructions and cover matrices with branch number 6 as well.

关键词： Registers Software Ciphers Computer architecture Encoding Hardware

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Fast fixed-point divider based on Newton-Raphson method and piecewise polynomial approximation

Fast fixed-point divider based on Newton-Raphson method and ...

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： A. Rodriguez-Garcia L. Pizano-Escalante R. Parra-Michel O. Longoria-Gandara J. Cortez Dept. of Electrical Engineering CINVESTAV-IPN Zapopan Mexico Dept. of Electronics Systems and Informatics ITESO Tlaquepaque Mexico Dept. of Engineering and Technology ITSON Mexico

Division is an operation extensively used in architectures for digital signal processing algorithms, which in portable devices require an implementation using fixed-point format. In this paper, a novel fixed-point divider is proposed. The divider architecture is based on a division algorithm that uses the reciprocal operation and a post-multiplication. In turn, reciprocal operation is based on the Newton-Raphson algorithm, where the seed is provided through piecewise polynomial approximation. Reciprocal operation is performed with only two clocks cycles and division operation requires only three clock cycles. A comparison between the proposed architecture and dividers based on coordinate rotation digital computer, shows that the proposed architecture achieves approximately 5-fold gain in execution time for applications in 50-100 MHz frequency range and higher signal-to-quantization-noise ratio.

关键词： Computer architecture Clocks Polynomials Approximation methods Hardware Accuracy Signal processing algorithms

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Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocation

Rerouting: Scalable NoC self-optimization by distributed har...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Jan Heisswolf Maximilian Singh Martin Kupper Ralf König Jürgen Becker Karlsruhe Institute of Technology Germany

Networks-on-Chip (NoC) are the most promising candidates for scalable communication infrastructures in manycore architectures. To ensure scalability, distributed management of communication resources needs to replace centralized approaches. Hence, distributed adaptive routing schemes in combination with selection strategies are used to take semi-optimal routing decisions according to the current NoC utilization. Once these routing decisions are taken for guaranteed service connections, which are established for longer periods, the load situation can change during their lifetime. For such connections taken routing decisions might be poor at a later point in time due to dynamically changing communication workload. The proposed hardware-based mechanism called rerouting reacts on changing load conditions and reallocates existing connections transparently. This balances the NoC load and allows to increase the number of guaranteed service connections. Throughput and delay of existing connections can also be improved by rerouting. The concept is investigated using synthetic traffic patterns and distributed video processing applications. ASIC and FPGA synthesis results are presented to investigate the implementation costs.

关键词： Routing Delays Ports (Computers) Switches Throughput Quality of service Magnetic heads

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Distributed execution of transmural electrophysiological imaging with CPU, GPU, and FPGA

Distributed execution of transmural electrophysiological ima...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Sam Skalicky Sonia Lopez Marcin Lukowiak Department of Computer Engineering Rochester Institute of Technology Rochester NY USA

One of the main challenges of using cutting edge medical imaging applications in the clinical setting is the large amount of data processing required. Many of these applications are based on linear algebra computations operating on large data sizes and their execution may require days in a standard CPU. Distributed heterogeneous systems are capable of improving the performance of applications by using the right computation-to-hardware mapping. To achieve high performance, hardware platforms are chosen to satisfy the needs of each computation with corresponding architectural features such as clock speed, number of parallel computational units, and memory bandwidth. In this paper we evaluate the performance benefits of using different hardware platforms to accelerate the execution of a transmural electro physiological imaging algorithm, targeting a standard CPU with GPU and FPGA accelerators. Using this cutting edge medical imaging application as a case study, we demonstrate the importance of making intelligent computation assignments for improved performance. We show that, depending on the size of the data structures the application works with, the usage of an FPGA to run certain computations can make a big difference: a heterogeneous system with all three hardware platforms (CPU+GPU+FPGA) can cut the execution time by half, compared to the best result using one single accelerator (CPU+GPU). In addition, our experimental results show that combining CPU, GPU, and FPGA platforms in a single system achieves a speedup of up to 62×, 2×, and 1605× compared to systems with a single CPU, GPU, or FPGA platform respectively.

关键词： Field programmable gate arrays Graphics processing units Matrix decomposition Hardware Computer architecture Imaging Bandwidth

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Hardware-software scalable architectures for Gaussian elimination over GF(2) and higher galois fields

Hardware-software scalable architectures for Gaussian elimin...

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3rd International conference on Pervasive Embedded computing and Communication Systems, PECCS 2013

作者： Saxena, Prateek Kumar, Vinay B.Y. Singh, Dilawar Narayanan, H. Patkar, Sachin B. Department of Electrical Engineering Indian Institute of Technology Bombay Mumbai India

ISBN: (纸本)9789898565433

Solving a System of Linear Equations over Finite Fields finds one of the most important practical applications, for instance, in problems arising in cryptanalysis and network coding among others. However, other than software-only approaches to acceleration, the amount of focus particularly towards hardware or hardware/ software based solutions is small, in comparison to that towards general linear equation solvers. We present scalable architectures for Gaussian elimination with pivoting over GF(2) and higher fields, both as custom extensions to commodity processors or as dedicated hardware for larger problems. In particular, we present: 1) Designs of components-Matrix Multiplication and 'Basis search and Inversion'-for Gaussian elimination over GF(2), prototyped as custom instruction extensions to Nios-ii on DE2-70 (DE2, 2008), which even with a 50MHz clock perform at ≈30 GOPS (billion GF(2) operations);and also report results for GF(28) or higher order matrix multiplication with about 20 GOPS performance at 200MBps. 2) A scalable extension of a previous design (Bogdanov et. al, 2006) for multiple fpgas and with ≈2.5 TrillionOPS performance at 5GBps bandwidth on a Virtex-5 FPGA.

关键词： Field programmable gate arrays (FPGA)

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An asynchronous bus bridge for partitioned multi-soc architectures on fpgas

An asynchronous bus bridge for partitioned multi-soc archite...

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International conference on Field Programmable Logic and applications

作者： Daniel Kliem Sven-Ole Voigt Institute for Reliable Computing Hamburg University of Technology Hamburg Germany

Recent FPGA families exhibit a bandwidth gap that is inverse to the widely known memory bottleneck of hardwired platforms: Behaviorally described soft processors are comparatively slow whereas fpgas offer high-throughput state-of-the-art memory attachments. We show that it is possible to take advantage of this bandwidth gap to host functionally partitioned safety- and security-critical software functions. Our proposed multisystem architecture instantiates multiple self-contained local systems on a reconfigurable platform that operates from a shared but partitioned memory. We benchmark and evaluate a novel asynchronous bus bridge and demonstrate that the asynchronous architecture is scalable both at run-time and during place-and-route.

关键词： Bridges Computer architecture Clocks Bandwidth Field programmable gate arrays Program processors Benchmark testing

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Acceleration of real-time Proximity Query for dynamic active constraints

Acceleration of real-time Proximity Query for dynamic active...

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IEEE International conference on Field-Programmable technology (FPT)

作者： Thomas C.P. Chau Ka-Wai Kwok Gary C.T. Chow Kuen Hung Tsoi Kit-Hang Lee Zion Tse Peter Y. K. Cheung Wayne Luk Department of Computing London UK Department of Mechanical Engineering The University of Hong Kong Hong Kong College of Engineering The University of Georgia Athens GA USA Department of Electrical and Electronic Engineering Imperial College London UK

Proximity Query (PQ) is a process to calculate the relative placement of objects. It is a critical task for many applications such as robot motion planning, but it is often too computationally demanding for real-time applications, particularly those involving human-robot collaborative control. This paper derives a PQ formulation which can support non-convex objects represented by meshes or cloud points. We optimise the proposed PQ for reconfigurable hardware by function transformation and reduced precision, resulting in a novel data structure and memory architecture for data streaming while maintaining the accuracy of results. Run-time reconfiguration is adopted for dynamic precision optimisation. Experimental results show that our optimised PQ implementation on a reconfigurable platform with four fpgas is 58 times faster than an optimised CPU implementation with 12 cores, 9 times faster than a GPU, and 3 times faster than a double precision implementation with four fpgas.

关键词： Field programmable gate arrays Mathematical model Equations Hardware Accuracy Optimization Robots

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An open-source SATA core for Virtex-4 fpgas

An open-source SATA core for Virtex-4 FPGAs

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IEEE International conference on Field-Programmable technology (FPT)

作者： Cory Gorman Paul Siqueira Russell Tessier Department of Electrical and Computer Engineering University of Massachusetts Amherst MA USA

In this demonstration, we present an open-source Serial ATA core designed for Virtex-4 fpgas. This core utilizes the RocketIO Multi-Gigabit Transceiver (MGT) of the Virtex-4 to interface with hard drives at SATA Generation 1 (SATA I, 1.5 Gb/s) and Generation 2 (SATA ii, 3.0 Gb/s) speeds. A full design hierarchy from host software to the physical layer is provided with the distribution to facilitate design use. A simple, FIFO interface allows for easy integration with other FPGA modules. The demonstration illustrates the correct write and read behavior of the core using a Xilinx ML405 board and a solid state disk. The peak transfer rate of the core for SATA I (130 MB/s) is demonstrated. Our goal for the demonstration is to educate the reconfigurable computing community regarding the availability of the core and to illustrate its capabilities.

关键词： Field programmable gate arrays Clocks Open source software Physical layer Protocols Transceivers Debugging

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Dreams: A Tool for the design of Dynamically reconfigurable Embedded and Modular Systems

Dreams: A Tool for the design of Dynamically Reconfigurable ...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Otero, Andres de la Torre, Eduardo Riesgo, Teresa Univ Politecn Madrid Ctr Elect Ind Madrid Spain

ISBN: (纸本)9781467329194;9781467329200

Dynamically reconfigurable Systems are attracting a growing interest, mainly due to the emergence of novel applications based on this technology. However, commercial tools do not provide enough flexibility to design solutions, while keeping an acceptable design productivity. In this paper, a novel design flow is proposed, targeting dynamically reconfigurable systems. It is fully supported by a tool called Dreams, which is able to implement flexible systems, starting from a set of netlists corresponding to the modules, as well as a system description provided by the user. The tool automatically post-processes the nets, implementing a solution for the communications between reconfigurable regions, as well as the handling of routing conflicts, by means of a custom router. Since the design process of every module and the static system are independent, the proposed flow is compatible with system upgrade at run-time. In this paper, a use case corresponding to the design of a highly regular and parallel mesh-type architecture is described, in order to show the architectural flexibility offered by the tool.

关键词： component FPGA Dynamic and Partial Reconfiguration Design Flow CAD Tool XDL

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