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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

共 418 条记录，以下是141-150 订阅

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Keynote 1 — The once and future FPGA: The confluence of configurable processing and reconfigurable technology

Keynote 1 — The once and future FPGA: The confluence of con...

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： Grant Martin Tensilica

Summary form only given. We want to consider the unification of hard computing resources with reconfigurable fabrics. This is a perennial topic in reconfigurable computing. A decade ago we had Altera Excalibur, Xilinx Virtex ii Pro, and on the small side, Stretch. Then processors started going very soft, with Nios, microBlaze and other soft-cores. Now we see new generations of hardened processors in fpgas, with hardened ARMs in Altera and Xilinx devices. But there are yet new opportunities to consider if we look at application-specific hardened processors in fpgas. Specialized signal processing cores built with configurable processor technology can complement the more general-purpose hardened control processors now available. This talk will review some history, paint a picture of what is possible today, and peer a little bit into the future.

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Design and implementation of Reed Solomon Decoder for 802.16 network using FPGA

Design and implementation of Reed Solomon Decoder for 802.16...

引用

2012 IEEE International conference on Signal Processing, computing and Control, ISPCC 2012

作者： Tiwari, Bhawna Mehra, Rajesh ECE Department Ideal Institute of Technology Ghaziabad India ECE Department NITTTR Chandigarh India

ISBN: (纸本)9781467313179

This paper presents a design and FPGA implementation of a reconfigurable FEC Decoder based on Reed Solomon Code for WiMax Network. The implementation, written in Very High Speed hardware description Language (VHDL) is based on Berlekamp Massey, Forney and Chein Algorithm. The 802.16 network standard recommends the use of Reed-Solomon code RS (255,239), which is implemented and discussed in this paper. It is targeted to be applied in a forward error correction system based on 802.16 network standard to improve the overall performance of the system. The objective of this work is to implement a Reed-Solomon VHDL code to measure the performance of the RS Decoder on Xilinx Virtex ii pro (xc2vp50-5-ff1148) and Xilinx Spartan 3e (xc3s500e-4-fg320) FPGA. The performance of the implemented RS codec on both fpgas will be compared. The performance metrics to be used are the area occupied by the design and the speed at which the design can run. © 2012 IEEE.

关键词： Field programmable gate arrays (FPGA)

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A multi-core FPGA-based SoC architecture with domain segregation

A multi-core FPGA-based SoC architecture with domain segrega...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Daniel Kliem Sven-Ole Voigt Institute for Reliable Computing Hamburg University of Technology Hamburg Germany

Nowadays, fpgas are sufficiently large to host not only single soft-core CPUs but a whole Multi-Processor System-on-a-Chip (MPSoC). They follow the recent trend of chip-multiprocessing. Given the requirement for domain segregation in safety and security related applications, we propose an FPGA-based architecture that achieves segregation by secure bus bridges. According to the SoC-paradigm, we use a single shared memory controller to reduce external component count. We pay special attention to performance evaluation and avoidance of temporal conflicts. The architecture is evaluated by dedicated bus observers using simulation and hardware prototypes and is finally benchmarked by running multiple isolated off-the-shelf Linux systems.

关键词： Bridges System-on-a-chip Radiation detectors Benchmark testing Field programmable gate arrays Clocks Computer architecture

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Design of parallel vector/scalar floating point co-processor for reconfigurable architecture

Design of parallel vector/scalar floating point co-processor...

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2012 International conference on computing, Electronics and Electrical Technologies, ICCEET 2012

作者： Manikandan, E. Karthigeyan, K.A. Immanuvel Arokia James, K. Department of EEE Veltech Multitech Dr.RR Dr. SR Engg. College Chennai India

ISBN: (纸本)9781467302111

Current FPGA soft processor systems use dedicated hardware modules or accelerators to speed up data-parallel applications. This work explores an alternative approach of using a soft vector processor as a general-purpose accelerator. Due to the complexity and expense of floating point hardware, these algorithms are usually converted to fixed point operations or implemented using floating-point emulation in software. As the technology advances, more and more homogeneous computational resources and fixed function embedded blocks are added to fpgas and hence implementation of floating point hardware becomes a feasible option. In this research we have implemented a high performance, autonomous floating point vector co-processor (FPVC) that works independently within an embedded processor system. We have presented a unified approach to vector and scalar computation, using a single register file for both scalar operands and vector elements. The FPVC is completely autonomous from the embedded processor(Softcore), exploiting parallelism and exhibiting greater speedup than alternative vector processors. The FPVC supports scalar computation so that loops can be executed independently of the main embedded processor. © 2012 IEEE.

关键词： Field programmable gate arrays (FPGA)

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A lightweight speculative and predicative scheme for hardware execution

A lightweight speculative and predicative scheme for hardwar...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Razvan Nane Vlad-Mihai Sima Koen Bertels Computer Engineering Laboratory Delft University of Technology Netherlands

If-conversion is a known software technique to speedup applications containing conditional expressions and targeting processors with predication support. However, the success of this scheme is highly dependent on the structure of the if-statements, i.e., if they are balanced or unbalanced, as well as on the path taken. Therefore, the predication scheme does not always provide a better execution time than the conventional jump scheme. In this paper, we present an algorithm that leverages the benefits of both jump and predication schemes adapted for hardware execution. The results show that performance degradation is not possible anymore for the unbalanced if-statements as well as a speedup for all test cases between 4% and 21%.

关键词： Hardware Engines Program processors Optimization Degradation Computer architecture Delay

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Design and analysis of layered coarse-grained reconfigurable architecture

Design and analysis of layered coarse-grained reconfigurable...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Zoltán Endre Rákossy Tejas Naphade Anupam Chattopadhyay Institute for Communication Technologies and Embedded Systems (ICE) RWTH Aachen University Germany Department of Electrical Engineering Indian Institute of Technology Bombay India

Coarse-grained reconfigurable architectures (CGRAs) represent an important class of programmable accelerators with a significant performance advantage for data-driven, systolic algorithms. In this paper, we present a novel CGRA where data access, data transport and execution are separately layered into dedicated, independent structures. The proposed architecture concept allows for independent control and optimization on each layer to address the storage access bottleneck, faced by state-of-the-art CGRAs. The architecture is programmable and the implementation is derived from a high-level language specification, allowing fast design exploration, debugging and simulation. Up to 50% run-time performance improvement and 5× area-time-energy product gain of the layered CGRA over a non-layered one is demonstrated with 2 case studies from demanding linear algebra applications.

关键词： Registers Arrays Pipelines Assembly Bandwidth Timing

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Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems

Dreams: A tool for the design of dynamically reconfigurable ...

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： Andrés Otero Eduardo de la Torre Teresa Riesgo Centro de Electrónica Industrial Universidad Politécnica de Madrid Madrid Spain

Dynamically reconfigurable Systems are attracting a growing interest, mainly due to the emergence of novel applications based on this technology. However, commercial tools do not provide enough flexibility to design solutions, while keeping an acceptable design productivity. In this paper, a novel design flow is proposed, targeting dynamically reconfigurable systems. It is fully supported by a tool called Dreams, which is able to implement flexible systems, starting from a set of netlists corresponding to the modules, as well as a system description provided by the user. The tool automatically post-processes the nets, implementing a solution for the communications between reconfigurable regions, as well as the handling of routing conflicts, by means of a custom router. Since the design process of every module and the static system are independent, the proposed flow is compatible with system upgrade at run-time. In this paper, a use case corresponding to the design of a highly regular and parallel mesh-type architecture is described, in order to show the architectural flexibility offered by the tool.

关键词： Routing Field programmable gate arrays Ports (Computers) Design automation Wires Data structures Hardware design languages

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Determination of on-chip temperature gradients on reconfigurable hardware

Determination of on-chip temperature gradients on reconfigur...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Carsten Tradowsky Enrique Cordero Thorsten Deuser Michael Hübner Jürgen Becker Institute for Information Processing Technology (ITIV) Karlsruhe Institute of Technology Germany Now at Chair for Embedded Systems in Information Technology (ESIT) Ruhr University of Bochum Germany

Nowadays, reconfigurable hardware is used in a broad range of use cases and applications. Therefore, hardware components need to operate reliably in a wide range of temperatures. The problem of heat dissipation is a widely discussed topic and has to be taken into account especially with the trend of smaller technologies being used to manufacture the chips. The uneven heat distribution and the temperature differences across the chip stress it in different ways so that an aging process could develop and contribute to a shorter lifespan of a product. One major problem is that on today's boards sensors occupy a relatively large amount of area on the chip. For this reason, the implementation of a monitoring process that is based on a simple design and does not consume too much power is proposed. This allows to determine uneven processes and would lead to the consequence to reconfigure the hardware for an optimal distribution of the heat. The paper proposes a method of on-chip temperature measurement and monitoring on reconfigurable hardware. The design explores an approach in which physical sensors are no longer needed. Additionally, the proposed system allows the measurement of on-chip temperature in any location of an FPGA. Subsequently, by placing the on-chip measurement system into strategic locations on the reconfigurable hardware, the presence of an on-chip temperature gradient is observed which could affect the reliability of critical designs.

关键词： Temperature measurement Radiation detectors Hardware Ring oscillators Time measurement System-on-a-chip Temperature

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Module relocation in Heterogeneous reconfigurable Systems-on-Chip using the Xilinx Isolation Design Flow

Module relocation in Heterogeneous Reconfigurable Systems-on...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： L. Gantel M.E.A Benkhelifa F. Lemonnier F. Verdier Embedded System Laboratory Thales Research and Technology Palaiseau France ETIS Laboratory CNRS UMR 8051 UCP / ENSEA Cergy-Pontoise France LEAT Laboratory CNRS UMR 7248 UNSA Sophia-Antipolis France

Heterogeneous reconfigurable Systems-on-Chip (HRSoC) contain as their name suggests, heterogeneous processing elements in a single chip. Namely, several processors, hardware accelerators as well as communication networks between all these components. In order to leverage the programming complexity of this kind of platform, applications are described with software threads, running on processors, and hardware threads, running on FPGA partitions. Combining techniques such as dynamic and partial reconfiguration and partial readback with the knowledge of the bitstream structure offer the ability to target several partitions using a unique configuration file. Such a feature permits to save critical memory resources. In this article, we propose to tackle the issue of designing fully independent partitions, and especially to avoid the routing conflicts which can occur when using the standard Xilinx FPGA design flow. To achieve the relocation process successfully, we propose a new design flow dedicated to the module relocation, using the standard tools and based on the Isolation Design Flow (IDF), a special flow provided by Xilinx for secure FPGA applications.

关键词： Instruction sets Hardware Field programmable gate arrays Routing Operating systems Context

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Design and implementation of Reed Solomon Decoder for 802.16 network using FPGA

Design and implementation of Reed Solomon Decoder for 802.16...

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IEEE International conference on Signal Processing, computing and Control (ISPCC)

作者： Bhawna Tiwari Rajesh Mehra ECE Department Ideal Institute of Technology Ghaziabad India ECE Department National Institute of Technical Teachers Training and Research Chandigarh India

关键词： Decoding Polynomials Field programmable gate arrays Forward error correction Reed-Solomon codes IEEE 802.16 Standards Mathematical model

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