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Design of parallel vector/scalar floating point co-processor for reconfigurable architecture

Design of parallel vector/scalar floating point co-processor...

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International conference on computing, Electronics and Electrical Technologies (ICCEET)

作者： E. Manikandan K.A. Karthigeyan K. Immanuvel Arokia James Department of EEE Veltech Multitech Dr. Rangarajan Dr. Sakunthala Engineering College Chennai India Department of ECE Veltech Multitech Dr. Rangarajan Dr. Sakunthala Engineering College Chennai India

Current FPGA soft processor systems use dedicated hardware modules or accelerators to speed up data-parallel applications. This work explores an alternative approach of using a soft vector processor as a general-purpose accelerator. Due to the complexity and expense of floating point hardware, these algorithms are usually converted to fixed point operations or implemented using floating-point emulation in software. As the technology advances, more and more homogeneous computational resources and fixed function embedded blocks are added to fpgas and hence implementation of floating point hardware becomes a feasible option. In this research we have implemented a high performance, autonomous floating point vector co-processor (FPVC) that works independently within an embedded processor system. We have presented a unified approach to vector and scalar computation, using a single register file for both scalar operands and vector elements. The FPVC is completely autonomous from the embedded processor(Softcore), exploiting parallelism and exhibiting greater speedup than alternative vector processors. The FPVC supports scalar computation so that loops can be executed independently of the main embedded processor.

关键词： Field programmable gate arrays Random access memory Vectors Registers Manuals Logic gates Computer architecture

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Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration

Novel Design Methods and a Tool Flow for Unleashing Dynamic ...

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IEEE International conference on Computational Science and Engineering, CSE

作者： K. Papadimitriou C. Pilato D. Pnevmatikatos M.D. Santambrogio C. Ciobanu T. Todman T. Becker T. Davidson X. Niu G. Gaydadjiev W. Luk D. Stroobandt Foundation for Research and Technology Hellas Greece Dipartimento di Elettronica e Informazione Politecnico di Milano Italy Chalmers University of Technology Sweden Imperial College London UK Ghent University-IBBT Belgium

During the last few years, there is an increasing interest in mixing software and hardware to serve efficiently different applications. This is due to the heterogeneity characterizing the tasks of an application which require the presence of resources from both worlds, software and hardware. Controlling effectively these resources through an integrated tool flow is a challenging problem and towards this direction only a few efforts exist. In fact, a framework that seamlessly exploits both resources of a platform for executing efficiently an application has not yet come into existence. Moreover, reconfigurable computing often incorporated in such platforms due to its high flexibility and customization, has not yet taken off due to the lack of exploiting its full capabilities. Thus, the capability of reconfigurable devices such as Field Programmable Gate Arrays (fpgas) to be dynamically reconfigured, i.e. reprogramming part of the chip while other parts of the same chip remain functional, has not yet taken off even in small-scale basis. The inherent difficulty in using the tools to control this technology has kept it back from being adopted by academia and industry alike. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a design methodology and a tool flow that will enable designers to implement effectively and easily a system specification on a platform combining software and reconfigurable resources. The FASTER framework accepts as input a high-level description of the application and the architectural details of the target platform, and through certain steps it can enable the full use of the capabilities of the platform, while at the same time it should be flexible enough so as to balance efficiently performance, power and area. One of the main novelties is the incorporation of partial reconfiguration as an explicit design concept at an early stage of the design flow. We target different applica

关键词： Hardware Runtime Software Field programmable gate arrays Design methodology Computer architecture Educational institutions

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Implementation of a reconfigurable computing system for space applications

Implementation of a reconfigurable computing system for spac...

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2011 International conference on System Science, Engineering Design and Manufacturing Informatization, ICSEM 2011

作者： Cai, Yimao Zhao, Yuanfu Lan, Lidong Beijing Microelectronics Technology Institute Beijing China

ISBN: (纸本)9781457702471

High reliability is usually the most important requirement in space applications. There is no hardware repair for them. Long mission times and harsh environment are a challenge for electronic circuits, and particular error mitigation techniques have to be implemented in order to be able to cope with the expected error effects. Always, Triple Modular Redundancy (TMR) is relied mostly to prevent SEUs from causing functional errors. And in recent decades, SRAM-based fpgas are used a lot in space for its high performance and flexibility. However, use of fpgas in space applications can also be challenging. They are too susceptible to transient faults, such as SEUs. Reconfiguration provides more possibilities for SRAM-based fpgas into space. reconfigurable technology solves the disadvantage that the TMR modules cannot heal the error themselves. Additionally, reconfiguration is an improvement in terms of resource utilization and costs. In this paper, TMR and reconfigurable computing are combined to level up the reliability of the space applications. The paper proposed a reconfigurable computing architecture based on a TMR system. A new kind of reconfigurable architecture using SoP (system-on-a- package) technology is presented. Also, a whole space application will be presented. © 2011 IEEE.

关键词： Fault tolerance

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Snake: An efficient strategy for the reuse of circuitry and partial computation results in high-performance reconfigurable computing

Snake: An efficient strategy for the reuse of circuitry and ...

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2011 International conference on reconfigurable computing and fpgas, ReConFig 2011

作者： Iturbe, Xabier Benkrid, Khaled Ebrahim, Ali Hong, Chuan Arslan, Tughrul Martinez, Imanol System Level Integration Group University of Edinburgh Edinburgh EH9 3JL United Kingdom Embedded System-on-Chip Group IKERLAN-IK4 Research Alliance Mondraǵn 20500 Basque Country Spain

ISBN: (纸本)9780769545516

In this paper we present "Snake", a novel technique for allocating and executing hardware tasks onto partially reconfigurable Xilinx fpgas. Snake permits to alleviate the bottleneck introduced by the Internal Configuration Access Port (ICAP) in Xilinx fpgas, by reusing both intermediate partial results and previously allocated pieces of circuitry. Moreover, Snake considers often neglected aspects in previous approaches when making allocation decisions, such as the technological constraints introduced by reconfigurable technology and inter-task communication issues. As a result of being a realistic solution its implementation using real FPGA hardware has been successful. We have checked its ability to reduce not only the overall execution time of a wide range of synthetic reconfigurable applications, but also time overheads in making allocation decisions in the first place. © 2011 IEEE.

关键词： Dynamic models

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GPU vs FPGA: Example application on white light interferometry

GPU vs FPGA: Example application on white light interferomet...

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2011 International conference on reconfigurable computing and fpgas, ReConFig 2011

作者： Pacholik, A. Müller, M. Fengler, W. Machleidt, T. Franke, K.-H. Computer Architecture and Embedded Systems Group Ilmenau University of Technology 98684 Ilmenau Germany Computer Graphics Group Ilmenau University of Technology 98684 Ilmenau Germany

ISBN: (纸本)9780769545516

High performance image processing applications area challenging field when targeting embedded processing. Field programmable gate arrays (FPGA) receive a growing interest as implementation platforms, but these solutions have to compete with the state of the art in image processing, which is codefined by graphics processing units (GPU). This paper provides a case study which analyzes the potential of embedded or hybrid implementation on FPGA and GPU for image stack processing in a white light interferometry (WLI) application. © 2011 IEEE.

关键词： Graphics processing unit

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Low-power reconfigurable component utilization in a high-level synthesis flow

Low-power reconfigurable component utilization in a high-lev...

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2011 International conference on reconfigurable computing and fpgas, ReConFig 2011

作者： Bekiaris, Dimitris Economakos, George Sotiriou-Xanthopoulos, Efstathios Soudris, Dimitrios National Technical University of Athens School of Electrical and Computer Engineering Microprocessors and Digital Systems Laboratory Heroon Polytechniou 9 GR-15780 Zografou Athens Greece

ISBN: (纸本)9780769545516

reconfigurable computing is a cost-effective alternative to technology shrinking in order to achieve higher performance in digital design, especially considering run time reconfiguration. Research in the field consists of new reconfigurable architectures, either coarse-grain or fine-grain, and new methodologies to map applications onto them. A special case of coarse-grain reconfigurable components are morphable multipliers, which use multiplexers to feed different inputs and form different connection schemes within the data path of conventional multipliers. These connection schemes form different components that can be utilized when the initial multiplier is idle. Morphable components offer performance improvements but the use of extra multiplexers impose power overheads. This paper applies two low-power design techniques, power gating and multi Vth components, for the design of low-power morphable multipliers. Experimentation with these multipliers in a high-level synthesis flow show that they can offer performance, area and power improvements compared to alternative architectures, making them valuable building blocks for hardware synthesis. © 2011 IEEE.

关键词： reconfigurable architectures

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dcTPM: A generic architecture for dynamic context management

dcTPM: A generic architecture for dynamic context management

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2011 International conference on reconfigurable computing and fpgas, ReConFig 2011

作者： Feller, Thomas Malipatlolla, Sunil Kasper, Michael Huss, Sorin A. Center for Advanced Security Research Darmstadt CASED Germany Fraunhofer Institute for Secure Information Technology Darmstadt Germany Integrated Circuits and Systems Lab. Technische Universität Darmstadt Germany

ISBN: (纸本)9780769545516

With the emergence of new technologies the requirements for trusted platforms are constantly changing. Thus, the current Trusted Platform Modules (TPMs) have to cope with issues they have not been designed for. One such deficit of current TPMs is the inability to support multiple stakeholders as in mobile computing, virtualization, and cloud computing applications. In such scenarios, a TPM has to attest the state of their applications on the platform to each stakeholder and to additionally protect their individual assets. Therefore, we present a novel architecture, called Dynamic-Context TPM (dcTPM), to satisfy the needs of each participant in multiple stakeholder applications. Though there exist related approaches in literature, they address only software-based TPM instances. In contrast, the architecture proposed in this paper supports not only software-based TPMs, but also dedicated hardware TPMs or a combination of both for each stakeholder. As an additional asset, the dcTPM architecture enables a dynamic exchange of contexts (TPM instances) without any modification of the underlying architecture. This architecture has been implemented as a proof-of-concept on top of a Xilinx Virtex-5 FPGA platform, demonstrating a test case with off-the-shelf hardware and software TPMs. © 2011 IEEE.

关键词： Software testing

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Enhancing the randomness of a combined true random number generator based on the ring oscillator sampling method

Enhancing the randomness of a combined true random number ge...

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2011 International conference on reconfigurable computing and fpgas, ReConFig 2011

作者： Jessa, Mieczyslaw Matuszewski, Lukasz Faculty of Electronics and Telecommunications Poznan University of Technology Poznan Poland

ISBN: (纸本)9780769545516

An efficient method for generating number sequences that pass all statistical tests is combining numbers produced by many independent generators. Excellent statistical properties are very important in many applications but they are not sufficient in cryptography. We need the unpredictability of numbers that ensures the irreproducibility of sequences by an attacker. This paper proposes a new method for enhancing the randomness of a combined true random number generator (TRNG) using jitter observed in ring oscillators (ROs). To enhance the quality of output streams, we use an auxiliary source of randomness (ASR) that perturbs signals produced by ROs. The increase of entropy is obtained by combining XOR bits produced by many biased RO-based TRNGs. It increases the degree of unpredictability but requires a measure of the quality of this process, which is different from statistical testing of time sequences. To assess the unpredictability of output bits, we used the restarts mechanism proposed in earlier papers. © 2011 IEEE.

关键词： Entropy

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Dynamic processor reconfiguration

Dynamic processor reconfiguration

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2011 International conference on reconfigurable computing and fpgas, ReConFig 2011

作者： Hübner, M. Tradowsky, C. Göhringer, D. Braun, L. Thoma, F. Henkel, J. Becker, J. Karlsruhe Institute of Technology - KIT Germany Fraunhofer IOSB Ettlingen Germany

ISBN: (纸本)9780769545516

General purpose processors provide a well performance with adequate power consumption for a huge bandwidth of applications in average. However, most embedded systems target a very narrow or even single application domain which would benefit from a specific processor, optimized for this scenario in order to gain performance and to reduce power consumption. But the development of application specific processors for each application is a time consuming task and often not feasible for developers due to the missing toolsets or experience in processor design. This paper introduces a novel approach for a processor core, which is able to adapt its micro architecture in relation to the application requirement. In general, the processor starts in a general purpose mode and migrates while run-time to a special purpose processor by adapting its micro architecture. The paper introduces this novel processor approach which is called i-core and presents first experimental results. © 2011 IEEE.

关键词： Electric power utilization

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2011 International conference on Field-Programmable technology, FPT 2011

2011 International Conference on Field-Programmable Technolo...

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2011 International conference on Field-Programmable technology, FPT 2011

ISBN: (纸本)9781457717406

The proceedings contain 65 papers. The topics discussed include: a self-healing autonomous neural network hardware for trustworthy biomedical systems;FPGA implementation of reconfigurable ADPLL network for distributed clock generation;a framework for verifying functional correctness in odin ii;an analysis of ring oscillator PUF behavior on fpgas;a low power technology mapping method for adaptive logic module;hydrate: hybrid reconfigurable architecture expressions;a novel architecture for a secure update of cryptographic engines on trusted platform module;interconnect-topology independent mapping algorithm for a coarse grained reconfigurable architecture;deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithm;use of embedded FPGA resources in implementations of 14 round 2 SHA-3 candidates;and constant power reconfigurable computing.

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