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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

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Hydrate: Hybrid reconfigurable architecture expressions

Hydrate: Hybrid reconfigurable architecture expressions

引用

2011 International conference on Field-Programmable technology, FPT 2011

作者： Yu, Chiwai Cox, Fred Luk, Wayne Cheung, Ray C.C. Department of Electronic Engineering City University of Hong Kong Hong Kong Hong Kong Department of Computing Imperial College London United Kingdom

ISBN: (纸本)9781457717406

This paper presents Hydrate (HYbriD reconfigurable ArchiTecture Expressions), a generic architecture description language for exploring hybrid FPGA designs. Hydrate is based on the XML architecture description for the VPR tool. These expressions consist of variable, repeat and conditional statements to allow flexible, reusable and readable description for FPGA architectures, without modifying the VPR core. Two case studies, involving modern FPGA and floating-point applications, are used to illustrate our approach. Compared with VPR5.0 and VPR6.0, the architecture file format adopted by Hydrate is often much smaller and easier to understand, and over 90% of file size reduction for complex fpgas can be achieved. Moreover, Hydrate is compatible with different versions of VPR, so that the powerful VPR tool flow can be used to explore future architectures. © 2011 IEEE.

关键词： reconfigurable architectures

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reconfigurable systems and flexible programming for hardware design, verification and software enablement for system-on-a-chip architectures

Reconfigurable systems and flexible programming for hardware...

引用

2011 International conference on reconfigurable computing and fpgas, ReConFig 2011

作者： Aylward, J. Crawford, C.H. Inoue, K. Lekuch, S. Muller, K. Nutter, M. Penner, H. Schleupen, K. Xenidis, J. IBM System and Technology Group Poughkeepsie NY United States IBM TJ Watson Research Center Yorktown Heights NY United States IBM Ireland Product Dist. Ltd. Muddart Ireland IBM Austin Research Labs. Austin TX United States

ISBN: (纸本)9780769545516

In this paper we provide a detailed description of a Field Programmable Gate Array (FPGA) based reconfigurable system which has been used in the development of a System on a Chip (SoC) processor and corresponding applications targeted for network computing appliances. The complexity of the processor, in terms of number of hardware threads (64), integrated on chip accelerators and network interfaces, combined with time to market requirements of the final system necessitated hardware verification and software development on pre-silicon systems that provided a high degree of architecture fidelity, reasonable time to completion for verification tests, and sufficient diagnosis tools for root cause analysis from processor logic to application design. To meet these requirements, we developed an FPGA based emulator which actually implemented the combined chip logic function by mapping it to FPGA equivalent gate functions. This system has the advantage over other simulation environments in that it has actual chip logic that can be executed at "real world speeds" e.g. MHz, rather than the traditional HDL simulators which are typically executed at 10 or 100's of KHz. Additional flexibility in terms of system verification, analysis and application development was provided by the development of a library OS based programming environment, Bare Metal Application (BMA), complimentary to both the FPGA based system as well as the actual silicon. The main contribution of this work was the development of a reconfigurable and flexible simulation system, both hardware and software which, to the best of our knowledge, provided the first heterogeneous multipurpose environment for silicon and software validation on a system with both general purpose cores and on board accelerators. © 2011 IEEE.

关键词： Integrated circuit design

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Implementing a safe embedded computing system in SRAM-based fpgas using IP cores: A case study based on the Altera NIOS-ii soft processor

Implementing a safe embedded computing system in SRAM-based ...

引用

IEEE Latin American Symposium on Circuits and Systems

作者： Perez Acle, Julio Reorda, Matteo Sonza Violante, Massimo Facultad de Ingeniería Universidad de la República Montevideo Uruguay Dip. Automatica e Informatica Politecnico di Torino Torino Italy

ISBN: (纸本)9781424494859

reconfigurable Field Programmable Gate Arrays (fpgas) are growing the attention of developers of mission- and safety-critical applications (e.g., aerospace ones), as they allow unprecedented levels of performance, which are making these devices particularly attractive as ASICs replacement, and as they offer the unique feature of in-the-field reconfiguration. However, the sensitivity of reconfigurable fpgas to ionizing radiation mandates the adoption of fault tolerant mitigation techniques that may impact heavily the FPGA resource usage. In this paper we consider time redundancy, that allows avoiding the high overhead that more traditional approaches like N-modular redundancy introduce, at an affordable cost in terms of application execution-time overhead. A single processor executes two instances of the same software sequentially;the two instances are segregated in their own memory space through a soft IP core that monitors the processor/memory interface for any violations. Moreover, the IP core checks for any processor functional interruption by means of a watchdog timer. Fault injection results are reported showing the characteristics of the proposed approach. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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reconfigurable FPGA-based unit for singular value decomposition of large m x n matrices

Reconfigurable FPGA-based unit for singular value decomposit...

引用

2011 International conference on reconfigurable computing and fpgas, ReConFig 2011

作者： Ledesma-Carrillo, Luis M. Cabal-Yepez, Eduardo Romero-Troncoso, Rene De J. Garcia-Perez, Arturo Osornio-Rios, Roque A. Carozzi, Tobia D. Division de Ingenierias Campus Irapuato-Salamanca Universidad de Guanajuato Carr. Salamanca-Valle km 3.5+1.8 36700 Salamanca Guanajuato Mexico Facultad de Ingenieria Campus San Juan del Rio Universidad Autonoma de Queretaro Rio Moctezuma 249 Col. San Cayetano 76807 San Juan del Rio Queretaro Mexico Onsala Space Observatory Chalmers University of Technology SE-439 92 Onsala Sweden

ISBN: (纸本)9780769545516

Singular value decomposition (SVD) allows the factorization of real or complex matrices providing quantitative information with fewer dimensions along which data points exhibit more variation. These days SVD computation is being used in numerous applications, and because of its importance, different approaches for SVD hardware computation have been proposed, however, their application is limited by the inherent SVD calculation complexity making it possible to analyze up to 8 x 8 matrices until now, complying certain constrains like symmetry. This paper presents a generic and novel FPGA-based hardware architecture for SVD computation on large m x n matrices utilizing Hestenes approach and one-side Jacobi rotations. Four different study cases (2 x 2, 8 x 7, 16 x 32, and 32 x 127 matrices) validate the performance of the FPGA-based computation unit reaching a maximum estimation error of 3.3718 % in the SVD estimation of a large matrix. © 2011 IEEE.

关键词： Singular value decomposition

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Design of a reconfigurable Coprocessor for Double Precision Floating Point Matrix Algorithms

引用

International conference on Information technology for Manufacturing Systems (ITMS 2011)

作者： Li, Shenglong Li, Zhaolin Zheng, Qingwei Tsinghua Univ Inst Microelect Beijing 100084 Peoples R China Tsinghua Univ Res Inst Informat Technol Tsinghua Natl Lab Informat Sci & Technol Beijing 100084 Peoples R China

ISBN: (纸本)9783037851494

Double precision floating point matrix operations are wildly used in a variety of engineering and scientific computing applications. However, it's inefficient to achieve these operations using software approaches on general purpose processors. In order to reduce the processing time and satisfy the real-time demand, a reconfigurable coprocessor for double precision floating point matrix algorithms is proposed in this paper. The coprocessor is embedded in a Multi-Processor System on Chip (MPSoC), cooperates with an ARM core and a DSP core for high-performance control and calculation. One algorithm in GPS applications is taken for example to illustrate the efficiency of the coprocessor proposed in this paper. The experiment result shows that the coprocessor can achieve speedup a factor of 50 for the quaternion algorithm of attitude solution in inertial navigation application compare with software execution time of a TI C6713 DSP. The coprocessor is implemented in SMIC 0.13 mu m CMOS technology, the synthesis time delay is 9.75ns, and the power consumption is 63.69 mW when it works at 100MHz.

关键词： reconfigurable Coprocessor Multi-Processor System on Chip Quaternion Algorithm Double Precision Floating Point Matrix Algorithms

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Performance optimization of CNFET for ultra-low power reconfigurable architecture 11

Performance optimization of CNFET for ultra-low power reconf...

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Proceedings of the 2011 International conference on Communication, computing & Security

作者： Pable, S.D. Hasan, Mohd Department of Electronics Engineering Zakir Husain College of Engineering and Technology Aligarh Muslim University Aligarh India

ISBN: (纸本)9781450304641

The designers of field programmable gate array (fpgas) always devote to optimize the chip performance. The fabrication cost of ASICs is rising exponentially in deep submicron and hence it is important to investigate ways of reducing FPGA power consumption so that they can also deploy in place of ASICs in portable energy constrained applications. Minimum energy delay point occurs in subthreshold region and subthreshold operation of circuits shows order of power saving over superthreshold circuits. Therefore, it is also important to investigate the possibility of extending the use of FPGA even in subthreshold region for ultra low power applications. This paper investigates the subthreshold performance of a basic FPGA building block-a Look up Table (LUT). It presents the performance optimization of CNFET based fully encoded three inputs LUT in deep submicron (DSM) region for delay, power dissipation and switching energy. Proposed multi-chirality LUT implementation shows significant advantages in delay as well as switching energy. Copyright © 2011 ACM.

关键词： Chirality

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Implementation of a reconfigurable computing system for space applications

Implementation of a reconfigurable computing system for spac...

引用

International conference on System Science, Engineering Design and Manufacturing Informatization (ICSEM)

作者： Yimao Cai Yuanfu Zhao Lidong Lan Beijing Microelectronics Technology Institute Beijing China

High reliability is usually the most important requirement in space applications. There is no hardware repair for them. Long mission times and harsh environment are a challenge for electronic circuits, and particular error mitigation techniques have to be implemented in order to be able to cope with the expected error effects. Always, Triple Modular Redundancy (TMR) is relied mostly to prevent SEUs from causing functional errors. And in recent decades, SRAM-based fpgas are used a lot in space for its high performance and flexibility. However, use of fpgas in space applications can also be challenging. They are too susceptible to transient faults, such as SEUs. Reconfiguration provides more possibilities for SRAM-based fpgas into space. reconfigurable technology solves the disadvantage that the TMR modules cannot heal the error themselves. Additionally, reconfiguration is an improvement in terms of resource utilization and costs. In this paper, TMR and reconfigurable computing are combined to level up the reliability of the space applications. The paper proposed a reconfigurable computing architecture based on a TMR system. A new kind of reconfigurable architecture using SoP (system-on-a-package) technology is presented. Also, a whole space application will be presented.

关键词： Tunneling magnetoresistance Reliability Irrigation Field programmable gate arrays Hardware Microelectronics

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Partially reconfigurable system-on-chips for adaptive fault tolerance

Partially reconfigurable system-on-chips for adaptive fault ...

引用

2011 International conference on Field-Programmable technology, FPT 2011

作者： Yousuf, Shaon Jacobs, Adam Gordon-Ross, Ann Department of Electrical and Computing Engineering University of Florida Gainesville FL 32611 United States

ISBN: (纸本)9781457717406

Due to the runtime flexibility of modern dynamically reconfigurable SRAM-based fpgas, FPGA devices have become an attractive platform for developing system-on-chips (SoCs) for space applications (space SoCs). However, since the FPGA's SRAM is highly susceptible to space radiation, system reliability is a primary concern for space SoCs. To maintain system reliability and mitigate space radiation effects, space SoCs must be designed with redundant copies of system functionality. Space SoCs must contain enough redundancy to ensure system reliability for the highest anticipated radiation level, which imposes a large area overhead. However, since radiation levels vary based on the system's orbital position, the system does not always require the highest level of redundancy. Space SoCs that can adapt the system redundancy based on the current radiation level can achieve more effective device utilization. In this paper, we present a flexible, FPGA-based, adaptive SoC for space system development. Our space SoC leverages partial reconfiguration to dynamically adapt the system's level of redundancy according to varying radiation levels. We present a software algorithm to manage the system's adaptability, implement the SoC on a Xilinx Virtex-5 device, and evaluate the SoC's resource utilization using the International Space Station's orbit. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Snake: An Efficient Strategy for the Reuse of Circuitry and Partial Computation Results in High-Performance reconfigurable computing

Snake: An Efficient Strategy for the Reuse of Circuitry and ...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Xabier Iturbe Khaled Benkrid Ali Ebrahim Chuan Hong Tughrul Arslan Imanol Martinez System Level Integration Group University of Edinburgh Edinburgh UK Embedded System-on-Chip Group IK4 Research Alliance Basque Spain

In this paper we present "Snake", a novel technique for allocating and executing hardware tasks onto partially reconfigurable Xilinx fpgas. Snake permits to alleviate the bottleneck introduced by the Internal Configuration Access Port (ICAP) in Xilinx fpgas, by reusing both intermediate partial results and previously allocated pieces of circuitry. Moreover, Snake considers often neglected aspects in previous approaches when making allocation decisions, such as the technological constraints introduced by reconfigurable technology and inter-task communication issues. As a result of being a realistic solution its implementation using real FPGA hardware has been successful. We have checked its ability to reduce not only the overall execution time of a wide range of synthetic reconfigurable applications, but also time overheads in making allocation decisions in the first place.

关键词： Field programmable gate arrays Hardware Resource management Computational modeling Clocks Performance evaluation Software

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GPU vs FPGA: Example Application on White Light Interferometry

GPU vs FPGA: Example Application on White Light Interferomet...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： A. Pacholik M. Muller W. Fengler T. Machleidt K.-H. Franke Computer Architecture and Embedded Systems Group Ilmenau University of Technology Ilmenau Germany Computer Graphics Group Ilmenau University of Technology Ilmenau Germany

High performance image processing applications area challenging field when targeting embedded processing. Field programmable gate arrays (FPGA) receive a growing interest as implementation platforms, but these solutions have to compete with the state of the art in image processing, which is codefined by graphics processing units (GPU). This paper provides a case study which analyzes the potential of embedded or hybrid implementation on FPGA and GPU for image stack processing in a white light interferometry (WLI) application.

关键词： Graphics processing unit Field programmable gate arrays Demodulation Image resolution Bandwidth Throughput Hardware

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