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dcTPM: A Generic Architecture for Dynamic Context Management

dcTPM: A Generic Architecture for Dynamic Context Management

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Thomas Feller Sunil Malipatlolla Michael Kasper Sorin A. Huss Integrated Circuits and Systems Laboratory Technische Universität Darmstadt Germany Fraunhofer Institute of Secure Information Technology Darmstadt Germany

With the emergence of new technologies the requirements for trusted platforms are constantly changing. Thus, the current Trusted Platform Modules (TPMs) have to cope with issues they have not been designed for. One such deficit of current TPMs is the inability to support multiple stakeholders as in mobile computing, virtualization, and cloud computing applications. In such scenarios, a TPM has to attest the state of their applications on the platform to each stakeholder and to additionally protect their individual assets. Therefore, we present a novel architecture, called Dynamic-Context TPM (dcTPM), to satisfy the needs of each participant in multiple stakeholder applications. Though there exist related approaches in literature, they address only software-based TPM instances. In contrast, the architecture proposed in this paper supports not only software-based TPMs, but also dedicated hardware TPMs or a combination of both for each stakeholder. As an additional asset, the dcTPM architecture enables a dynamic exchange of contexts (TPM instances) without any modification of the underlying architecture. This architecture has been implemented as a proof-of-concept on top of a Xilinx Virtex-5 FPGA platform, demonstrating a test case with off-the-shelf hardware and software TPMs.

关键词： Context Computer architecture Hardware Field programmable gate arrays Software Protocols Security

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Low-Power reconfigurable Component Utilization in a High-Level Synthesis Flow

Low-Power Reconfigurable Component Utilization in a High-Lev...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Dimitris Bekiaris George Economakos Efstathios Sotiriou-Xanthopoulos Dimitrios Soudris School of Electrical and Computer Engineering Microprocessors and Digital Systems Laboratory National and Technical University of Athens Athens Greece

reconfigurable computing is a cost-effective alternative to technology shrinking in order to achieve higher performance in digital design, especially considering run time reconfiguration. Research in the field consists of new reconfigurable architectures, either coarse-grain or fine-grain, and new methodologies to map applications onto them. A special case of coarse-grain reconfigurable components are morphable multipliers, which use multiplexers to feed different inputs and form different connection schemes within the data path of conventional multipliers. These connection schemes form different components that can be utilized when the initial multiplier is idle. Morphable components offer performance improvements but the use of extra multiplexers impose power overheads. This paper applies two low-power design techniques, power gating and multi V th components, for the design of low-power morphable multipliers. Experimentation with these multipliers in a high-level synthesis flow show that they can offer performance, area and power improvements compared to alternative architectures, making them valuable building blocks for hardware synthesis.

关键词： Multiplexing Adders Computer architecture Hardware Timing Sparks Microprocessors

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Enhancing the Randomness of a Combined True Random Number Generator Based on the Ring Oscillator Sampling Method

Enhancing the Randomness of a Combined True Random Number Ge...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Mieczyslaw Jessa Lukasz Matuszewski Faculty of Electronics and Telecommunications Poznan University of Technology Poznan Poland

An efficient method for generating number sequences that pass all statistical tests is combining numbers produced by many independent generators. Excellent statistical properties are very important in many applications but they are not sufficient in cryptography. We need the unpredictability of numbers that ensures the irreproducibility of sequences by an attacker. This paper proposes a new method for enhancing the randomness of a combined true random number generator (TRNG) using jitter observed in ring oscillators (ROs). To enhance the quality of output streams, we use an auxiliary source of randomness (ASR) that perturbs signals produced by ROs. The increase of entropy is obtained by combining XOR bits produced by many biased RO-based TRNGs. It increases the degree of unpredictability but requires a measure of the quality of this process, which is different from statistical testing of time sequences. To assess the unpredictability of output bits, we used the restarts mechanism proposed in earlier papers.

关键词： Generators Ring oscillators Field programmable gate arrays Cryptography Entropy NIST

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Dynamic Processor Reconfiguration

Dynamic Processor Reconfiguration

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： M. Hubner C. Tradowsky D. Gohringer L. Braun F. Thoma J. Henkel J. Becker Karlsruhe Institute of Technology Germany Fraunhofer IOSB Ettlingen Germany

General purpose processors provide a well performance with adequate power consumption for a huge bandwidth of applications in average. However, most embedded systems target a very narrow or even single application domain which would benefit from a specific processor, optimized for this scenario in order to gain performance and to reduce power consumption. But the development of application specific processors for each application is a time consuming task and often not feasible for developers due to the missing toolsets or experience in processor design. This paper introduces a novel approach for a processor core, which is able to adapt its micro architecture in relation to the application requirement. In general, the processor starts in a general purpose mode and migrates while run-time to a special purpose processor by adapting its micro architecture. The paper introduces this novel processor approach which is called i-core and presents first experimental results.

关键词： Pipelines Microarchitecture Computer architecture Power demand Hardware conferences USA Councils

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Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function

Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical ...

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： Yohei Hori Hyunho Kang Toshihiro Katashita Akashi Satoh Research Center of Information Security (RCIS) National Institute of Advanced Industrial Science and Technology Tsukuba Japan

A physical unclonable function (PUF) with a novel hardware architecture called Pseudo-LFSR PUF (PL-PUF) is developed. The structure of the PL-PUF is based on LFSR but it actually is large combinational logic. The long feedback signal of the PL-PUF effectively extracts the device variation, and consequently the output IDs generated in the different devices become completely dissimilar. The advantages of the PL-PUF are that (1) the size of the circuit is small since it simply consists of inverters and a few XOR gates, (2) it efficiently outputs a long-bit ID since all n bits of the ID are simultaneously output from a single n-bit challenge, and (3) the challenge-response mapping of PL-PUF can be easily changed without modifying its hardware structure. The reliability of the PL-PUF is also examined in terms of False Acceptance Rate (FAR) and False Rejection Rate (FRR) through the experimentation using fpgas. The empirical results show that the intra-device Hamming distance among IDs generated in the same PL-PUF is quite small, the inter-device Hamming distance among IDs in different PL-PUFs is sufficiently large. As a consequent, it is demonstrated that the PL-PUF has quite low FAR/FRR and is quite effective for device identification and other security-sensitive applications. This paper describes the structure of the PL-PUF in detail and presents the experimental results of the performance evaluation using Virtex-5 fpgas.

关键词： Field programmable gate arrays High definition video Reliability Performance evaluation Hamming distance Clocks Security

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reconfigurable FPGA-Based Unit for Singular Value Decomposition of Large m x n Matrices

Reconfigurable FPGA-Based Unit for Singular Value Decomposit...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Luis M. Ledesma-Carrillo Eduardo Cabal-Yepez Rene de J. Romero-Troncoso Arturo Garcia-Perez Roque A. Osornio-Rios Tobia D. Carozzi HSPdigital - CA Telematica Universidad de Guanajuato / Carr. Salamanca-Valle km 3.5+ 1.8 Salamanca Guanajuato Mexico Universidad de Guanajuato Guanajuato Guanajuato MX HSPdigital - CA Mecatronica Universidad Autonoma de Queretaro San Juan del Rio Queretaro Mexico Onsala Space Observatory Chalmers University of Technology Sweden Onsala Sweden

Singular value decomposition (SVD) allows the factorization of real or complex matrices providing quantitative information with fewer dimensions along which data points exhibit more variation. These days SVD computation is being used in numerous applications, and because of its importance, different approaches for SVD hardware computation have been proposed, however, their application is limited by the inherent SVD calculation complexity making it possible to analyze up to 8 × 8 matrices until now, complying certain constrains like symmetry. This paper presents a generic and novel FPGA-based hardware architecture for SVD computation on large m × n matrices utilizing Hestenes approach and one-side Jacobi rotations. Four different study cases (2 × 2, 8 × 7, 16 × 32, and 32 × 127 matrices) validate the performance of the FPGA-based computation unit reaching a maximum estimation error of 3.3718% in the SVD estimation of a large matrix.

关键词： Jacobian matrices Hardware Matrix decomposition Field programmable gate arrays Symmetric matrices Random access memory Computer architecture

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reconfigurable Systems and Flexible Programming for Hardware Design, Verification and Software Enablement for System-on-a-Chip Architectures

Reconfigurable Systems and Flexible Programming for Hardware...

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： J. Aylward C.H. Crawford K. Inoue S. Lekuch K. Muller M. Nutter H. Penner K. Schleupen J. Xenidis IBM System and Technology Group in Poughkeepsie NY USA IBM TJ Watson Research Center Yorktown Heights NY USA IBM TJ Watson Research Center Yorktown Heights NY IBM Ireland Product Dist Ltd Muddart Ireland IBM Austin Research Laboratories TX USA IBM Austin Research Labs Austin TX

In this paper we provide a detailed description of a Field Programmable Gate Array (FPGA) based reconfigurable system which has been used in the development of a System on a Chip (SoC) processor and corresponding applications targeted for network computing appliances. The complexity of the processor, in terms of number of hardware threads (64), integrated on chip accelerators and network interfaces, combined with time to market requirements of the final system necessitated hardware verification and software development on pre-silicon systems that provided a high degree of architecture fidelity, reasonable time to completion for verification tests, and sufficient diagnosis tools for root cause analysis from processor logic to application design. To meet these requirements, we developed an FPGA based emulator which actually implemented the combined chip logic function by mapping it to FPGA equivalent gate functions. This system has the advantage over other simulation environments in that it has actual chip logic that can be executed at "real world speeds" e.g. MHz, rather than the traditional HDL simulators which are typically executed at 10 or 100's of KHz. Additional flexibility in terms of system verification, analysis and application development was provided by the development of a library OS based programming environment, Bare Metal Application (BMA), complimentary to both the FPGA based system as well as the actual silicon. The main contribution of this work was the development of a reconfigurable and flexible simulation system, both hardware and software which, to the best of our knowledge, provided the first heterogeneous multipurpose environment for silicon and software validation on a system with both general purpose cores and on board accelerators.

关键词： Field programmable gate arrays

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Formulation-level design space exploration for partially reconfigurable fpgas

Formulation-level design space exploration for partially rec...

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IEEE International conference on Field-Programmable technology (FPT)

作者： Rohit Kumar Ann Gordon-Ross NSF Center for High-Performance Reconfigurable Computing (CHREC) University of Florida Gainesville FL USA

Exploiting the benefits afforded by runtime partial reconfiguration (PR) on modern field-programmable gate arrays (fpgas)requires PR-capable applications and associated PR-architectures, both of which are challenging tasks due to competing implementation metrics(e.g., area, power, operating frequency, etc.) and results in unmanageable design spaces. PR design space exploration (DSE) techniques and tools assist designers in efficiently and effectively exploring this design space. This paper presents the first, to the best of our knowledge, formulation-level PR DSE tool - FoRSE. FoRSE leverages the application's PR-architecture and mathematical FPGA device models and vendor-specified PR technology to generate Pareto-optimal sets of PR-floorplans and devices based on designer-designated implementation metrics. FoRSE can prune an application's implementation design space by three to four orders of magnitude in approximately 15 seconds.

关键词： Measurement Field programmable gate arrays Space exploration Probes Digital signal processing Algorithm design and analysis Mathematical model

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Partially reconfigurable system-on-chips for adaptive fault tolerance

Partially reconfigurable system-on-chips for adaptive fault ...

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IEEE International conference on Field-Programmable technology (FPT)

作者： Shaon Yousuf Adam Jacobs Ann Gordon-Ross NSF Center for High-Performance Reconfigurable Computing (CHREC) Department of Electrical and Computing Engineering University of Florida Gainesville FL USA

Due to the runtime flexibility of modern dynamically reconfigurable SRAM-based fpgas, FPGA devices have become an attractive platform for developing system-on-chips (SoCs) for space applications (space SoCs). However, since the FPGA's SRAM is highly susceptible to space radiation, system reliability is a primary concern for space SoCs. To maintain system reliability and mitigate space radiation effects, space SoCs must be designed with redundant copies of system functionality. Space SoCs must contain enough redundancy to ensure system reliability for the highest anticipated radiation level, which imposes a large area overhead. However, since radiation levels vary based on the system's orbital position, the system does not always require the highest level of redundancy. Space SoCs that can adapt the system redundancy based on the current radiation level can achieve more effective device utilization. In this paper, we present a flexible, FPGA-based, adaptive SoC for space system development. Our space SoC leverages partial reconfiguration to dynamically adapt the system's level of redundancy according to varying radiation levels. We present a software algorithm to manage the system's adaptability, implement the SoC on a Xilinx Virtex-5 device, and evaluate the SoC's resource utilization using the International Space Station's orbit.

关键词： System-on-a-chip Space vehicles Field programmable gate arrays Hardware Redundancy Software

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Hydrate: Hybrid reconfigurable Architecture Expressions

Hydrate: Hybrid Reconfigurable Architecture Expressions

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IEEE International conference on Field-Programmable technology (FPT)

作者： ChiWai Yu Fred Cox Wayne Luk Ray C. C. Cheung Department of Electronic Engineering City University of Hong Kong Hong Kong China Department of Computing Imperial College London UK

This paper presents Hydrate (HYbriD reconfigurable ArchiTecture Expressions), a generic architecture description language for exploring hybrid FPGA designs. Hydrate is based on the XML architecture description for the VPR tool. These expressions consist of variable, repeat and conditional statements to allow flexible, reusable and readable description for FPGA architectures, without modifying the VPR core. Two case studies, involving modern FPGA and floating-point applications, are used to illustrate our approach. Compared with VPR5.0 and VPR6.0, the architecture file format adopted by Hydrate is often much smaller and easier to understand, and over 90% of file size reduction for complex fpgas can be achieved. Moreover, Hydrate is compatible with different versions of VPR, so that the powerful VPR tool flow can be used to explore future architectures.

关键词： Field programmable gate arrays Reactive power XML Delay Syntactics Routing Design automation

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