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Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays

作者： Mingjie Lin Shaoyi Cheng John Wawrzynek University of California at Berkeley Berkeley CA USA

ISBN: (纸本)9781450305549

Truly unleashing the computing potential of fpgas, as well as widening their applicability, demands alleviating cumbersome HDL programming and relieving laborious manual optimization. Towards this end, we propose a Many-core Approach to reconfigurable computing (MARC) that enables efficient high-performance computing for applications expressed with imperative programming languages such as C/C++ without constructing FPGA computing machines from scratch when targeting various applications within the same or similar problem domains. A MARC system achieves high computing performance by leveraging a many-core architectural template, sophisticated logic synthesizing techniques, and state-of-art compiler optimization technology. In addition, MARC exploits abundant special FPGA resources such as distributed block memories and DSP blocks to implement complete single-chip high efficiency many-core microarchitectures. The key benefits of MARC include (i) allowing programmers to easily express parallelism through a high-level programming language, (ii) supporting coarse-grain multithreading and dataflow-style fine-grain threading while permitting bit-level resource control, and (iii) greatly reducing the effort required to re-purpose the hardware system for different algorithms or different applications.

关键词： computing fpga template many-core

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FPGA Design of an Automatic Target Generation Process for Hyperspectral Image Analysis

FPGA Design of an Automatic Target Generation Process for Hy...

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International conference on Parallel and Distributed Systems (ICPADS)

作者： Sergio Bernabe Sebasti´n Lopez Antonio Plaza Roberto Sarmiento Pablo Garcia Rodriguez Hyperspectral Computing Laboratory Department of Technology of Computers and Communications University of Extremadura Caceres Spain Institute for Applied Microelectronics (IUMA) University of Las Palmas de Gran Canaria Tafira Baja Spain Grupo de Ingeniería de Medios (GIM) University of Extremadura Caceres Spain

Onboard processing of remotely sensed hyper spectral data is a highly desirable goal in many applications. For this purpose, compact reconfigurable hardware modules such as field programmable gate arrays (fpgas) are widely used. In this paper, we develop a new implementation of an automatic target generation process (ATGP) for hyper spectral images. Our implementation is based on a design methodology that starts from a high-level description in Matlab (or alternative C/C++) and obtains a register transfer level (RTL) description that can be ported to fpgas. In order to validate our new implementation, we develop a quantitative and comparative study using two different FPGA architectures: Xilinx Virtex-5 and Altera Stratix-iiI Altera. Experimental results have been obtained in the context of a real application focused on the detection of mineral components over the Cup rite mining district (Nevada), using hyper spectral data collected by NASA's Airborne Visible Infra-Red Imaging Spectrometer (AVIRIS). Our experimental results indicate that the proposed implementation can achieve peak frequency designs above 200MHz in the considered fpgas, in addition to satisfactory results in terms of target detection accuracy and parallel performance. This represents a step forward towards the design of real-time onboard implementations of hyper spectral image analysis algorithms.

关键词： Field programmable gate arrays Hyperspectral imaging Algorithm design and analysis Hardware Vectors Image analysis

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FPGA-Array with Bandwidth-Reduction Mechanism for Scalable and Power-Efficient Numerical Simulations Based on Finite Difference Methods

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ACM TRANSACTIONS ON reconfigurable technology AND SYSTEMS 2010年第4期3卷 1–35页

作者： Sano, Kentaro Wang Luzhou Hatsuda, Yoshiaki iizuka, Takanori Yamamoto, Satoru Tohoku Univ Grad Sch Informat Sci Aoba Ku Sendai Miyagi 9808579 Japan

For scientific numerical simulation that requires a relatively high ratio of data access to computation, the scalability of memory bandwidth is the key to performance improvement, and therefore custom-computing machines (CCMs) are one of the promising approaches to provide bandwidth-aware structures tailored for individual applications. In this article, we propose a scalable FPGA-array with bandwidth-reduction mechanism (BRM) to implement high-performance and power-efficient CCMs for scientific simulations based on finite difference methods. With the FPGA-array, we construct a systolic computational-memory array (SCMA), which is given a minimum of programmability to provide flexibility and high productivity for various computing kernels and boundary computations. Since the systolic computational-memory architecture of SCMA provides scalability of both memory bandwidth and arithmetic performance according to the array size, we introduce a homogeneously partitioning approach to the SCMA so that it is extensible over a 1D or 2D array of fpgas connected with a mesh network. To satisfy the bandwidth requirement of inter-FPGA communication, we propose BRM based on time-division multiplexing. BRM decreases the required number of communication channels between the adjacent fpgas at the cost of delay cycles. We formulate the trade-off between bandwidth and delay of inter-FPGA data-transfer with BRM. To demonstrate feasibility and evaluate performance quantitatively, we design and implement the SCMA of 192 processing elements over two ALTERA Stratix ii fpgas. The implemented SCMA running at 106MHz has the peak performance of 40.7 GFlops in single precision. We demonstrate that the SCMA achieves the sustained performances of 32.8 to 35.7 GFlops for three benchmark computations with high utilization of computing units. The SCMA has complete scalability to the increasing number of fpgas due to the highly localized computation and communication. In addition, we also demonstrate t

关键词： Design Experimentation Performance Finite difference methods fpgas reconfigurable computing scalable array

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Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics applications

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ACM TRANSACTIONS ON reconfigurable technology AND SYSTEMS 2010年第1期4卷 1–22页

作者： Lanuzza, M. Zicari, P. Frustaci, F. Perri, S. Corsonello, P. Univ Calabria Dept Elect Comp Sci & Syst I-87036 Arcavacata Di Rende CS Italy

This article presents a novel configuration scrubbing core, used for internal detection and correction of radiation-induced configuration single and multiple bit errors, without requiring external scrubbing. The proposed technique combines the benefits of fast radiation-induced fault detection with fast restoration of the device functionality and small area and power overheads. Experimental results demonstrate that the novel approach significantly improves the availability in hostile radiation environments of FPGA-based designs. When implemented using a Xilinx XC2V1000 Virtex-ii device, the presented technique detects and corrects single bit upsets and double, triple and quadruple multi bit upsets, occupying just 1488 slices and dissipating less than 30 mW at a 50MHz running frequency.

关键词： Design reconfigurable computing Xilinx fpgas space and avionics applications

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FPGA implementation of OFDM transceiver for a 60GHz wireless mobile radio system

FPGA implementation of OFDM transceiver for a 60GHz wireless...

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International conference on reconfigurable computing and fpgas

作者： Sobaihi, Khaled Hammoudeh, Akram Scammell, David Faculty of Advanced Technology University of Glamorgan United Kingdom

ISBN: (纸本)9780769543147

Orthogonal Frequency Division Multiplexing (OFDM) has been adopted by most wireless and wired communication standards;these include wireless Local Area Networks (LANs) HyperLan2, 802.11a, broadband wireless (802.16) and lately the 802.15.3c for millimetre wave communications. In parallel, Field-Programmable Gate Arrays (fpgas) have become an alternative for the implementation of those standards, due to their increased capabilities (speed and resources). This work introduces the design and performance evaluation of an OFDM transceiver, implemented on a FPGA platform for applications on a wireless millimetre wave radio system, operating around 60GHz. © 2010 IEEE.

关键词： Millimeter waves

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Issues on building an MPI cluster on Microblaze

Issues on building an MPI cluster on Microblaze

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2010 International conference on reconfigurable computing and fpgas, ReConFig 2010

作者： Díaz-Martín, Juan-Carlos Gutiérrez, Carolina Gómez-Tostón Fácila, Álvaro Cortés Rico-Gallego, Juan-Antonio Dept. of Computer Technology and Communications University of Extremadura Cáceres Spain Dept. of Computing and Telematic Systems Engineering University of Extremadura Cáceres Spain

ISBN: (纸本)9780769543147

MPI is the traditional paradigm to parallelize applications for High Performance computing environments. AzequiaMPI is an implementation of the MPI-1.3 standard. Its thread-based architecture enables it to run on high-end HPC machines as well as on embedded environments as soft-core processor in fpgas. This article describes the experience of building a maintainable cluster of fourteen popular Xilinx XUP2-Pro FPGA development boards around the PetaLinux/Microblaze base. Figures on the AzequiaMPI performance are given. © 2010 IEEE.

关键词： Field programmable gate arrays (FPGA)

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A runtime profiler: Toward virtualization of polymorphic computing platforms

A runtime profiler: Toward virtualization of polymorphic com...

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International conference on reconfigurable computing and fpgas

作者： Mushtaq, Hamid Sabeghi, Mojtaba Bertels, Koen Computer Engineering Laboratory Delft University of Technology Delft Netherlands

ISBN: (纸本)9780769543147

Runtime multitasking support on reconfigurable Computers requires complicated resource management techniques in which the FPGA area has to be shared between multiple concurrent tasks dynamically. Such a resource allocation mechanism needs to know the current configuration and load of the system in order to decide about the allocation of the resources. In such systems, a runtime profiler is an important tool which can give vital information about the running applications on the system. In this paper, we present the design and implementation of a runtime profiler which is responsible to produce statistics about the code running on the system. We have performed a set of experiments in order to show the overhead of our proposed profiler. The evaluation results show that the overhead imposed by the profiler is less than 1.5% of the total execution time and the information generated by the profiler is almost as accurate as a design time profiler such as gprof. © 2010 IEEE.

关键词： Virtualization

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Accelerating 2D FFT with non-power-of-two problem size on FPGA

Accelerating 2D FFT with non-power-of-two problem size on FP...

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International conference on reconfigurable computing and fpgas

作者： Wang, Wendi Duan, Bo Zhang, Chunming Zhang, Peiheng Sun, Ninghui High Performance Computer Research Center Institute of Computing Technology Chinese Academy of Sciences China Graduate University of Chinese Academy of Sciences China

ISBN: (纸本)9780769543147

The emergence of embedded and multimedia applications, which have a data-centric favor to them, have great influences on the design methodology of future systems. The 2D FFT is of particular importance to these applications. In this paper, leveraging the reconfigurable features of off-the-shelf fpgas, we propose a stream architecture that is suitable for accelerating 2D FFT with variable and non-power-of-two problem size. The system is built upon the concept of coarse-grained and application-specific pipeline and is optimized for 2D and real data FFT specifically. Separating data flow from computing flow and providing hardware support for data flow permutation involved in 2D FFT, our design outperforms previous work by 1.8 ∼ 21 times. Moreover, when facing real data, the speed will further increase by nearly 100%. To increase designer productivity, we reinforced traditional HDL-based hardware design flow with High-Level Synthesis concept. The prototyping system on a customized FPGA-based accelerator card can operate in 200MHz stably. © 2010 IEEE.

关键词： Fast Fourier transforms

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MARC: A many-core approach to reconfigurable computing

MARC: A many-core approach to reconfigurable computing

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International conference on reconfigurable computing and fpgas

作者： Lebedev, Ilia Cheng, Shaoyi Doupnik, Austin Martin, James Fletcher, Christopher Burke, Daniel Lin, Mingjie Wawrzynek, John Department of EECS University of California Berkeley CA 94704 United States

ISBN: (纸本)9780769543147

We present a Many-core Approach to Re-configurable computing (MARC), enabling efficient high-performance computing for applications expressed using parallel programming models such as OpenCL. The MARC system exploits abundant special FPGA resources such as distributed block memories and DSP blocks to implement complete single-chip high efficiency many-core microarchitectures. The key benefits of MARC are that it (i) allows programmers to easily express parallelism through the API defined in a high-level programming language, (ii) supports coarse-grain multithreading and dataflow-style fine-grain threading while permitting bit-level resource control, and (iii) greatly reduces the effort required to re-purpose the hardware system for different algorithms or different applications. A MARC prototype machine with 48 processing nodes was implemented using a Virtex-5 (XCV5LX155T-2) FPGA for a well known Bayesian network inference problem. We compare the runtime of the MARC machine against a manually optimized implementation. With fully synthesized application-specific processing cores, our MARC machine comes within a factor of 3 of the performance of a fully optimized FPGA solution but with a considerable reduction in development effort and a significant increase in retargetability. © 2010 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Design and implementation of a heterogeneous high-performance computing framework using dynamic and partial reconfigurable fpgas

Design and implementation of a heterogeneous high-performanc...

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10th IEEE International conference on Computer and Information technology, CIT-2010, 7th IEEE International conference on Embedded Software and Systems, ICESS-2010, 10th IEEE Int. Conf. Scalable computing and Communications, ScalCom-2010

作者： Zhang, Xingjun Ding, Yanfei Huang, Yiyuan Dong, Xiaoshe School of Electronic and Information Engineering Xi'an Jiaotong University Xi'an 710049 China

ISBN: (纸本)9780769541082

Integrating reconfigurable computing with high-performance computing, exploiting reconfigurable hardware with their advantages to make up for the inadequacy of the existing high-performance computers had gradually become the high-performance computing solutions and trends. Based on comprehensively investigating the reconfigurable technologies, the paper presented a high-performance computing scheme in which the general-purpose processing nodes are connected to the dynamic partial reconfigurable computing nodes through the high-speed network. Using module-based partial reconfiguration design method, a FPGA based dynamic and partial reconfigurable computing node is designed. This node has the ability to do dynamic and partial reconfiguration and can load different computing units according to the different requirements. Dynamic partial reconfigurable computing node integrated microprocessor, memory, network interface, reconfigurable computing module, interface module are designed and implemented. The experimental results show that the system can achieve more functions with fewer resources;and the reconfigurable computing node can nicely complete the task and the system performance is effectively improved. © 2010 IEEE.

关键词： reconfigurable hardware

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