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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

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RO-SVD: A reconfigurable Hardware Copyright Protection Framework for AIGC applications 35

RO-SVD: A Reconfigurable Hardware Copyright Protection Frame...

引用

35th IEEE International conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Ran, Zhuoheng Abdelgawad, Muhammad A. A. Zhang, Zekai Cheung, Ray C. C. Yan, Hong City Univ Hong Kong Dept Elect Engn Hong Kong Peoples R China City Univ Hong Kong Ctr Intelligent Multidimens Data Anal Hong Kong Peoples R China

ISBN: (纸本)9798350349641;9798350349634

The dramatic surge in the utilisation of generative artificial intelligence (GenAI) underscores the need for a secure and efficient mechanism to responsibly manage, use and disseminate multi-dimensional data generated by artificial intelligence (AI). In this paper, we propose a blockchain-based copyright traceability framework called ring oscillator-singular value decomposition (RO-SVD), which introduces decomposition computing to approximate low-rank matrices generated from hardware entropy sources and establishes an AI-generated content (AIGC) copyright traceability mechanism at the device level. By leveraging the parallelism and reconfigurability of field-programmable gate arrays (fpgas), our framework can be easily constructed on existing AI-accelerated devices and provide a low-cost solution to emerging copyright issues of AIGC. We developed a hardware-software (HW/SW) co-design prototype based on comprehensive analysis and on-board experiments with multiple AI-applicable fpgas. Using AI-generated images as a case study, our framework demonstrated effectiveness and emphasised customisation, unpredictability, efficiency, management and reconfigurability. To the best of our knowledge, this is the first practical hardware study discussing and implementing copyright traceability specifically for AI-generated content.

关键词： AI-generated content copyright protection singular value decomposition (SVD) blockchain nanofabrication AI security low-power AI

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reconfigurable Distributed FPGA Cluster Design for Deep Learning Accelerators

Reconfigurable Distributed FPGA Cluster Design for Deep Lear...

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2023 IEEE International conference on Electro Information technology, eIT 2023

作者： Johnson, Hans Fang, Tianyang Perez-Vicente, Alejandro Saniie, Jafar Research Laboratory Department of Electrical and Computer Engineering ChicagoIL United States

ISBN: (纸本)9781665493765

We propose a distributed system based on low-power embedded fpgas designed for edge computing applications focused on exploring distributing scheduling optimizations for Deep Learning (DL) workloads to obtain the best performance regarding latency and power efficiency. Our cluster was modular throughout the experiment, and we have implementations that consist of up to 12 Zynq-7020 chip-based boards as well as 5 UltraScale+ MPSoC FPGA boards connected through an ethernet switch, and the cluster will evaluate configurable Deep Learning Accelerator (DLA) Versatile Tensor Accelerator (VTA). This adaptable distributed architecture is distinguished by its capacity to evaluate and manage neural network workloads in numerous configurations which enables users to conduct multiple experiments tailored to their specific application needs. The proposed system can simultaneously execute diverse Neural Network (NN) models, arrange the computation graph in a pipeline structure, and manually allocate greater resources to the most computationally intensive layers of the NN graph. © 2023 IEEE.

关键词： Field programmable gate arrays (FPGA)

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ILP Based Mapping for Elastic CGRAs 29

ILP Based Mapping for Elastic CGRAs

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29th IEEE International conference on Embedded and Real-Time computing Systems and applications, RTCSA 2023

作者： Saito, Makoto Kojima, Takuya Takase, Hideki Nakamura, Hiroshi Graduate School of Information Science and Technology The University of Tokyo Tokyo Japan

ISBN: (纸本)9798350337860

In recent years, the emergence of deep learning and the need for big data analysis have created a demand for computers with high computational performance and energy efficiency. Since conventional ASICs and general-purpose CPUs cannot meet this requirement, domain-specific architectures that constrain applications are currently the focus of attention. Coarse-Grained reconfigurable Architecture (CGRA), one of the domain-specific architectures, is attracting attention because it is superior to CPUs and fpgas in terms of computational performance and power efficiency [1]. As depicted in Fig. 1, CGRA comprises a two-dimensional array of Processing Elements (PEs) and provides flexibility to change the instructions executed on the PEs and the connections between them, depending on the software being executed. On the other hand, the mapping problem for CGRA is an NP-complete problem, and there exist tradeoffs between solution accuracy and execution time. For real time applications, it is indispensable to shorten the mapping time. Thus, in this study, we propose an Integer Linear Programming (ILP) based mapping method for Elastic CGRA that aims to shorten mapping time while preserving solution accuracy. We have also implemented and preliminary evaluated the proposed method. © 2023 IEEE.

关键词： Mapping

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Cloud and Sensor-based Automation using Field Programmable Gate Array (FPGA) 14

Cloud and Sensor-based Automation using Field Programmable G...

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14th International conference on Advances in computing, Control, and Telecommunication Technologies, ACT 2023

作者： Chauhan, Aditya Patil, Shreyas S. Agrawal, Anita Jain, Aakash Chugh, Rishabh M. Reddy, K.S. Praneeth Department of Electrical and Electronics Engineering Birla Institute of Technology and Science-Pilani K.K Birla Goa Campus NH-17B Goa Zuarinagar403726 India

Cloud automation is one of the most promising and upcoming applications of IoT [1], as it allows users to control and monitor their environment remotely. Adopting the Internet of Things (IoT) in the automation industry has created an amazing opportunity to develop intelligent, automated systems. These systems can improve users' energy efficiency, security, and convenience. However, most automation systems based on microcontrollers may not be able to handle the complex and various tasks required in a modern environment. Field Programmable Gate Arrays (fpgas) replace microcontrollers, providing a more powerful, flexible, and scalable solution for the latest automation systems [2]. fpgas can perform multiple functions simultaneously, making them ideal for managing large amounts of sensor data and controlling signals in real-time. Moreover, fpgas are reconfigurable, enabling custom application creation and new features catering to the user’s specific needs. The ecosystem can also include voice assistants and AI-powered systems to learn user preferences and automate tasks. To create an effective ecosystem, devices must be compatible and communicate through a standard protocol like Bluetooth, Zigbee, Z-Wave, or Wi-Fi [13]. The ecosystem should also protect user privacy. A well-designed ecosystem can simplify daily tasks, increase comfort and convenience, and provide peace of mind by allowing users to monitor and control their systems remotely. © Grenze Scientific Society, 2023.

关键词： Internet of things

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ELEVATE: Optimal Scheduling of Time-Sensitive Tasks on the Heterogeneous reconfigurable Edge

ELEVATE: Optimal Scheduling of Time-Sensitive Tasks on the H...

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International conference on Network Protocols

作者： Ingo Hoyer Tarek Zaarour Ahmed Khalid Alexander Utz Karsten Seidl Ken Brown Ahmed H. Zahran Fraunhofer IMS Duisburg Germany Dell Research Dell Technologies Ireland Department of Electronic Components and Circuits University of Duisburg-Essen Duisburg Germany School of Computer Science & Information Technology University College Cork (UCC) Ireland

ISBN: (数字)9798350351712

ISBN: (纸本)9798350351729

Edge computing is evolving to include heterogeneous compute nodes with distinct characteristics. Graphic processing units (GPU) and field-programmable gate arrays (FPGA) can execute demanding deep learning (DL) tasks while meeting the deadlines of time-sensitive applications. However, fpgas require reconfiguration to execute different tasks. In this paper, we first demonstrate that fpgas can be reconfigured in real-time. Additionally, we propose ELEVATE as a novel scheduling algorithm for reconfigurable heterogeneous edge computing platforms targeting Industry 4.0 post-production quality control. ELEVATE design focusses on optimising the reconfiguration of the FPGA unit for heterogeneous quality inspection tasks. Our simulations indicate that ELEVATE reduces task waiting time by up to two orders of magnitude and achieves energy savings of up to 25 % compared to a statically configured FPGA unit.

关键词： Protocols Scheduling algorithms Graphics processing units Quality control Optimal scheduling Inspection Real-time systems Fourth Industrial Revolution Field programmable gate arrays Edge computing

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Fpga-based reconfigurable architectures for dsp computations 1st

Fpga-based reconfigurable architectures for dsp computations

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1st International conference on Frontiers in Smart Systems Technologies, ICFSST 2019

作者： Mazher Iqbal, J.L. Manikandan, T. Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology Avadi Chennai India Rajalakshmi Engineering College Chennai India

ISBN: (纸本)9789811550287

With extensive usage of Field Programmable Gate Arrays (fpgas), a reconfigurable computing platform enhances the wide variety of Digital Signal Processing (DSP) applications using Lookup Table (LUT), Flip-Flop, and multiplexers. reconfigurable computation using memory becomes a subject of current research. fpgas can be reprogrammed an unlimited number of times in which various DSP algorithms can be executed on a single hardware device, just as many different software algorithms can run on a conventional processor. The general architectures for DSP consist of a reconfigurable interconnection, Computational Elements (CEs), and memory. This article discusses on the CE architectures based on Memory (CEMs) and Serial arithmetic (CESs). reconfigurable computing based on memory is much faster, reliable, and, hence the computation using memory requires less delay and power. The CEMs perform multiplication and addition using LUT and the CESs perform computation using serial arithmetic’s. The results of the CESs, CEMs, and the computational reuse processing elements are compared. The architectures design based on CEMs significantly improves the performance of the previously reported results in terms of speed, area, and power using Xilinx Virtex-ii FPGA, and Xilinx Vivado software. © Springer Nature Singapore Pte Ltd 2021.

关键词： Digital signal processing

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Towards Automated FPGA Compilation of Spiking Neural Networks

Towards Automated FPGA Compilation of Spiking Neural Network...

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IEEE International conference on Artificial Intelligence Circuits and Systems (AICAS)

作者： Ayan Shymyrbay Mohammed E. Fouda Ahmed Eltawil Department of ECE CEMSE Division King Abdullah University of Science and Technology Thuwal Saudi Arabia Rain Neuromorphics Inc. San Francisco CA USA

ISBN: (数字)9798350383638

ISBN: (纸本)9798350383645

Edge computing and the Internet of Things (IoT) have created a growing demand for low-cost and low-power field programmable gate arrays (fpgas) to facilitate rapid and efficient processing. At the same time, spiking neural networks (SNNs) have gained popularity for their capacity to replicate biological processes and efficiently handle temporal data, making them a favorable choice in various IoT applications. However, designers must possess a comprehensive knowledge of FPGA architecture and programming methodologies to fully exploit the potential of fpgas for SNN implementations. In this work, we propose SpiComp framework aiming to automate the implementation of SNNs on fpgas, leveraging their reconfigurable nature and high efficiency without requiring domain expertise. Results show that the SNN implementations produced by the framework achieve high throughput and have a small energy footprint compared to other implementations in the literature while providing design automation.

关键词： Design automation Circuits and systems Spiking neural networks Computer architecture Logic gates Programming Throughput

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FLOWER: A Comprehensive Dataflow Compiler for High-Level Synthesis 20

FLOWER: A Comprehensive Dataflow Compiler for High-Level Syn...

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20th International conference on Field-Programmable technology (ICFPT)

作者： Amiri, Puya Perard-Gayot, Arsene Membarth, Richard Slusallek, Philipp Leissa, Roland Hack, Sebastian German Res Ctr Artificial Intelligence DFKI Bremen Germany TH Ingolstadt THI Res Inst AImot Bavaria Ingolstadt Germany Univ Mannheim Sch Business Informat & Math WIM Mannheim Germany Saarland Univ UdS Saarbrucken Germany

ISBN: (纸本)9781665420105

fpgas have found their way into data centers as accelerator cards, making reconfigurable computing more accessible for high-performance applications. At the same time, new high-level synthesis compilers like Xilinx Vitis and runtime libraries such as XRT attract software programmers into the reconfigurable domain. While software programmers are familiar with task-level and data-parallel programming, fpgas often require different types of parallelism. For example, data-driven parallelism is mandatory to obtain satisfactory hardware designs for pipelined dataflow architectures. However, software programmers are often not acquainted with dataflow architectures-resulting in poor hardware designs. In this work we present FLOWER, a comprehensive compiler infrastructure that provides automatic canonical transformations for high-level synthesis from a domain-specific library. This allows programmers to focus on algorithm implementations rather than low-level optimizations for dataflow architectures. We show that FLOWER allows to synthesize efficient implementations for high-performance streaming applications targeting Systemon-Chip and FPGA accelerator cards, in the context of image processing and computer vision.

关键词： high-level synthesis dataflow compiler FPGA transformations high-performance computing

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FPGA Based Hardware Accelerator for Bio-Informatics applications

FPGA Based Hardware Accelerator for Bio-Informatics Applicat...

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Innovation in technology (ASIANCON), Asian conference on

作者： Akash Kate Deepti Khurge Electronics and Telecommunication Engineering Pimpri-Chinchwad College of Engineering Pune India

We present the design and implementation of an FPGA-based accelerator for bioinformatics applications in this paper. To process large amounts of data generated by next generation sequencing (NGS) technologies, bioinformatics applications require high-performance computing capabilities. Because of their parallel processing capabilities and reconfigurable hardware, fpgas are a promising solution for accelerating bioinformatics applications. To achieve high throughput and low latency, the proposed accelerator architecture employs parallelism and pipelining. The FPGA accelerator's performance is compared to software implementations on a CPU. The results of the experiments show that the FPGA accelerator outperforms the CPU implementation.

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Using neuro-accelerators on fpgas in collaborative robotics tasks 2

Using neuro-accelerators on FPGAs in collaborative robotics ...

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conference on Optical Instrument Science, technology, and applications ii Held as Part of SPIE Optical System Design conference

作者： Zelensky, A. Semenishchev, E. Alepko, A. Abdullin, T. Ilyukhin, Y. Voronin, V. Moscow State Univ Technol STANKIN Moscow Russia

ISBN: (数字)9781510645974

ISBN: (纸本)9781510645974;9781510645967

The article discusses the implementation of a hardware neuroaccelerator based on fpgas of the Cyclone IV series with 115,000 logical elements. An assessment of the requirements for the hardware resources of the computing platform is given. The features of the implementation of the neural network in the tasks of cognitive robotics and industrial production have been investigated in order to improve safety in the interaction of a robot and a person.

关键词： convolutional neural network multilayer perceptron FPGA neuro accelerator image detection

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