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10th IEEE International conference on Computer and Information technology, CIT-2010, 7th IEEE International conference on Embedded Software and Systems, ICESS-2010, 10th IEEE Int. Conf. Scalable computing and Communications, ScalCom-2010

作者： Yang, Jie Yan, Like Ju, Lihan Wen, Yuan Zhang, Shaobin Chen, Tianzhou Zhejiang University-Intel Technology Center College of Computer Science Zhejiang University Hangzhou Zhejiang 310027 China

ISBN: (纸本)9780769541082

reconfigurable computing based on fpgas (Field Programmable Gate Arrays) has been a promising solution to improve the performance with high flexibility. However, the physical capacity limitation of fpgas prevents its wide adoption in real world. In this paper, a homogeneous NoC*based FPGA architecture is proposed, in which reconfigurable and I/O resources are interconnected via NoC so that reconfigurable modules can be placed anywhere once enough space available. Meanwhile, a virtual FPGA is proposed with which over large circuit can be implemented on a limited capacity FPGA. The experiment verified that our approach can provide more flexible reconfiguration, and combing NOC on FPGA, the resource utilization increased within 44.7%- 53.5% because of the fragment in CRs benefit from such kind of dynamic partial configuration. © 2010 IEEE.

关键词： Network-on-chip

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SeqHive: A reconfigurable computer cluster for genome re-sequencing

SeqHive: A reconfigurable computer cluster for genome re-seq...

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20th International conference on Field Programmable Logic and applications, FPL 2010

作者： Stevens, Kristian Chen, Henry Filiba, Terry McMahon, Peter Song, Yun S. Department of Computer Science University of California Davis Davis CA 95616 United States Berkeley Wireless Research Center 2108 Allston Way Berkeley CA 94704 United States Department of Electrical Engineering Stanford University Stanford CA 94305 United States Department of Electrical Engineering and Computer Sciences UC Berkeley Berkeley CA 94720 United States

ISBN: (纸本)9780769541792

We demonstrate how Field Programmable Gate Arrays (fpgas) may be used to address the computing challenges associated with assembling genome sequences from recent ultra-high-throughput sequencing technologies. Advances in sequencing technology allow researchers to generate immense amounts of raw data in the form of short reads with high error rates. A prerequisite to effectively utilizing this data for most applications is accurate alignment to a reference genome. While dynamic programming (DP) alignment algorithms are generally avoided on conventional architectures due to their computational complexity, they can be tailored for efficient implementation on systolic architectures. We describe and implement the first system capable of assembling large genomes using DP. We implemented application-specific DP algorithms for aligning data from ultra-high-throughput sequencers in a reconfigurable computing cluster. To obtain the necessary throughput while maintaining scoring integrity, we extended the compact encoding scheme of Lipton and Lopresti for our application. Each FPGA is capable of rapidly aligning multiple reads in parallel against a long reference genome. The reconfigurable cluster proves to be scalable and capable of processing real world datasets with a sustained performance of 11 tera cell updates per second. We examine the advantages and practicality of our system by benchmarking real genomic data from a large sequencing project. Our exhaustive validation confirms that application specific computing hardware can provide more accurate results than current heuristic methods and remain practical. While directly addressing the important problem of genomic assembly, particularly in circumstances where error rates or evolutionary divergence is high, the methods presented are also relevant to many other current applications for this type of data. © 2010 IEEE.

关键词： Dynamic programming

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Non-instruction fetch-based architecture reduces almost 100% of the dynamic power and energy

Non-instruction fetch-based architecture reduces almost 100%...

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作者： Renbi, Abdelghani Lindh, Lennart Delsing, Jerker Eislab Luleå University of Technology Sweden Embedded Systems Department Jönköping University Sweden

ISBN: (纸本)9780769543314

This paper demonstrates the benefit of fpgas for better power and energy efficiency when exploited for noninstruction fetch-based architecture. By replacing load/store architecture by non-instruction fetch-based designs for matrix multiplication, we reduced almost 100% of the dynamic power. Hence reconfigurable computing is the potential key to saving energy in battery-powered embedded systems and to solve the dissipated power dilemma, as the heat becomes the bottleneck of traditional high frequency processors. If the same strategy is applied to mainstream computers and data center servers, we will not only reduce electricity bills but we will also contribute to greener computing by improving the IT sector's CO2 emissions. The work involves three different designs, which multiply two matrices A and B of nxn 32-bit items and store the result in C matrix of nxn 64-bit items. The first two designs employ a single-purpose processor with different number of storage registers 2n and 2n2 and the third design uses a computer system piloted by NIOS ii/e processor with on-chip memory. The designs were captured in VHDL language and prototyped on an Altera Cyclone ii EP2C35F672C6 device. Both synthesis and place&route steps were performed with Quartus ii 6.0 Web Edition. The experiments were made on Altera DE2 board. In this paper we have also clarified further the power estimation error of Altera power estimation tools, which we have evaluated in [1]. © 2010 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Issues on Building an MPI Cluster on Microblaze

Issues on Building an MPI Cluster on Microblaze

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Juan-Carlos Diaz-Martin Carolina Gómez-Tostón Gutiérrez Álvaro Cortés Fácila Juan-Antonio Rico-Gallego Dept. of Computer Technology and Communications University of Extremadura Cáceres Spain Dept. of Computing and Telematic Systems Engineering University of Extremadura Cáceres Spain

MPI is the traditional paradigm to parallelize applications for High Performance computing environments. AzequiaMPI is an implementation of the MPI-1.3 standard. Its thread-based architecture enables it to run on high-end HPC machines as well as on embedded environments as soft-core processor in fpgas. This article describes the experience of building a maintainable cluster of fourteen popular Xilinx XUP2-Pro FPGA development boards around the PetaLinux/Micro blaze base. Figures on the AzequiaMPI performance are given.

关键词： Field programmable gate arrays Servers IP networks Multicore processing Ethernet networks Bandwidth Protocols

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FPGA Implementation of OFDM Transceiver for a 60GHz Wireless Mobile Radio System

FPGA Implementation of OFDM Transceiver for a 60GHz Wireless...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Khaled Sobaihi Akram Hammoudeh David Scammell Faculty of Advanced Technology University of Glamorgan UK

Orthogonal Frequency Division Multiplexing (OFDM) has been adopted by most wireless and wired communication standards, these include wireless Local Area Networks (LANs) HyperLan2, 802.11a, broadband wireless (802.16) and lately the 802.15.3c for millimetre wave communications. In parallel, Field-Programmable Gate Arrays (fpgas) have become an alternative for the implementation of those standards, due to their increased capabilities (speed and resources). This work introduces the design and performance evaluation of an OFDM transceiver, implemented on a FPGA platform for applications on a wireless millimetre wave radio system, operating around 60GHz.

关键词： OFDM Field programmable gate arrays Transceivers Generators Digital signal processing Wireless communication AWGN

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MARC: A Many-Core Approach to reconfigurable computing

MARC: A Many-Core Approach to Reconfigurable Computing

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Ilia Lebedev Shaoyi Cheng Austin Doupnik James Martin Christopher Fletcher Daniel Burke Mingjie Lin John Wawrzynek Department of EECS University of California Berkeley CA USA

We present a Many-core Approach to reconfigurable computing (MARC), enabling efficient high-performance computing for applications expressed using parallel programming models such as OpenCL. The MARC system exploits abundant special FPGA resources such as distributed block memories and DSP blocks to implement complete single-chip high efficiency many-core micro architectures. The key benefits of MARC are that it (i) allows programmers to easily express parallelism through the API defined in a high-level programming language, (ii) supports coarse-grain multithreading and dataflow-style fine-grain threading while permitting bit-level resource control, and (iii) greatly reduces the effort required to re-purpose the hardware system for different algorithms or different applications. A MARC prototype machine with 48 processing nodes was implemented using a Virtex-5 (XCV5LX155T-2) FPGA for a well known Bayesian network inference problem. We compare the runtime of the MARC machine against a manually optimized implementation. With fully synthesized application-specific processing cores, our MARC machine comes within a factor of 3 of the performance of a fully optimized FPGA solution but with a considerable reduction in development effort and a significant increase in retarget ability.

关键词： Field programmable gate arrays Instruction sets Kernel Random access memory Hardware Performance evaluation

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Accelerating 2D FFT with Non-Power-of-Two Problem Size on FPGA

Accelerating 2D FFT with Non-Power-of-Two Problem Size on FP...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Wendi Wang Bo Duan Chunming Zhang Peiheng Zhang Ninghui Sun Chinese Academy of Sciences Beijing Beijing CN High Performance Computer Research Center Institute of Computing Technology Chinese Academy and Sciences China

The emergence of embedded and multimedia applications, which have a data-centric favor to them, have great influences on the design methodology of future systems. The 2D FFT is of particular importance to these applications. In this paper, leveraging the reconfigurable features of off-the-shelf fpgas, we propose a stream architecture that is suitable for accelerating 2D FFT with variable and non-power-of-two problem size. The system is built upon the concept of coarse-grained and application-specific pipeline and is optimized for 2D and real data FFT specifically. Separating data flow from computing flow and providing hardware support for data flow permutation involved in 2D FFT, our design outperforms previous work by 1:8 21 times. Moreover, when facing real data, the speed will further increase by nearly 100%. To increase designer productivity, we reinforced traditional HDL-based hardware design flow with High-Level Synthesis concept. The prototyping system on a customized FPGA-based accelerator card can operate in 200MHz stably.

关键词： Computer architecture Field programmable gate arrays Random access memory Algorithm design and analysis Acceleration Discrete Fourier transforms

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FPGA-Array with Bandwidth-Reduction Mechanism for Scalable and Power-Efficient Numerical Simulations Based on Finite Difference Methods

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ACM TRANSACTIONS ON reconfigurable technology AND SYSTEMS 2010年第4期3卷 21-21页

作者： Sano, Kentaro Wang Luzhou Hatsuda, Yoshiaki iizuka, Takanori Yamamoto, Satoru Tohoku Univ Grad Sch Informat Sci Aoba Ku Sendai Miyagi 9808579 Japan

For scientific numerical simulation that requires a relatively high ratio of data access to computation, the scalability of memory bandwidth is the key to performance improvement, and therefore custom-computing machines (CCMs) are one of the promising approaches to provide bandwidth-aware structures tailored for individual applications. In this article, we propose a scalable FPGA-array with bandwidth-reduction mechanism (BRM) to implement high-performance and power-efficient CCMs for scientific simulations based on finite difference methods. With the FPGA-array, we construct a systolic computational-memory array (SCMA), which is given a minimum of programmability to provide flexibility and high productivity for various computing kernels and boundary computations. Since the systolic computational-memory architecture of SCMA provides scalability of both memory bandwidth and arithmetic performance according to the array size, we introduce a homogeneously partitioning approach to the SCMA so that it is extensible over a 1D or 2D array of fpgas connected with a mesh network. To satisfy the bandwidth requirement of inter-FPGA communication, we propose BRM based on time-division multiplexing. BRM decreases the required number of communication channels between the adjacent fpgas at the cost of delay cycles. We formulate the trade-off between bandwidth and delay of inter-FPGA data-transfer with BRM. To demonstrate feasibility and evaluate performance quantitatively, we design and implement the SCMA of 192 processing elements over two ALTERA Stratix ii fpgas. The implemented SCMA running at 106MHz has the peak performance of 40.7 GFlops in single precision. We demonstrate that the SCMA achieves the sustained performances of 32.8 to 35.7 GFlops for three benchmark computations with high utilization of computing units. The SCMA has complete scalability to the increasing number of fpgas due to the highly localized computation and communication. In addition, we also demonstrate t

关键词： Design Experimentation Performance Finite difference methods fpgas reconfigurable computing scalable array

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Multi-channel Driving Systems for Therapeutic applications Based-on Focused Ultrasound

Multi-channel Driving Systems for Therapeutic Applications B...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： J. Pindter-Medina S. Pichardo L. Curiel A.D. Garcia-Garcia J.E. Chong-Quero Research and Graduate Studies Atizapan de Zaragoza Estado de Mexico ITESM-CEM Mexico Electrical Engineering Lakehead University Thunder Bay ONT Canada Department of Electrical and Electronic Engineering Atizapan de Zaragoza Edo.de Mex. ITESM-CEM Mexico

The present study shows the feasibility of using Field Programmable Gate Arrays (FPGA) for the generation of independent signals intended to drive therapeutic devices based on focused ultrasound. These devices require hundreds of independent signals where it is required to control amplitude, phase and frequency of sinusoidal signals. Since Magnetic Resonance Imaging (MRI) is used often for the guidance of the therapy, the driving electronics has to be compatible with the MRI environment. The design of the system and results from first tests are shown. Results indicated that up-to 80 independent signals can be generated using a Cyclone ii unit (Altera, San Jose, California, US) and this number can be increased with a different family of FPGA or using a matrix of fpgas.

关键词： Field programmable gate arrays Ultrasonic imaging Magnetic resonance imaging Frequency control Transducers Medical treatment Phased arrays

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reconfigurable computing technology Used for Modern Scientific applications

Reconfigurable Computing Technology Used for Modern Scientif...

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2010 2nd International conference on Education technology and Computer(第二届IEEE教育技术与计算机国际会议 ICETC 2010)

作者： M.Aqeel Iqbal Shoab A.Khan Uzma Saeed Awan Dept.of SE FUIEMS Pakistan Dept.of CE College of E & ME NUST Pakistan Dept.of CS CUT Abbottabad Pakistan Dept.of CE College of E & ME NUST Pakistan

The inventions of modern scientific applications of recent era have introduced many new dimensions of the computing technology. Conventionally two basic types of the computing technologies have ever been in use including the computing based on the extremely high speed application specific integrated circuits (ASICs) and the computing based on the most flexible programmable general purpose processors (GPPs). So far these domains of computing have been targeting the two different types of the applications including the high speed applications with the use of the ASICs and versatile programmable applications with the use of the GPPs. But the recent scientific research has introduced many new application areas which are requiring both the high speed as well as flexibility of the computing platforms. In order to fulfill these requirements of such type of applications, the reconfigurable computing technology has been introduced. reconfigurable computing is intended to fill the gape between the ASICs and GPPs by integrating the both technologies on a single chip. This research paper introduces the role of reconfigurable computing in the execution of such a type of newly born modern scientific applications.

关键词： reconfigurable computing ASICs fpgas Configuration Bits/reams reconfigurable Units

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