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reconfigurable computing technology Used for Modern Scientific applications

Reconfigurable Computing Technology Used for Modern Scientif...

2010 2nd International conference on Education technology and Computer(第二届IEEE教育技术与计算机国际会议 ICETC 2010)

作者： M.Aqeel Iqbal Shoab A.Khan Uzma Saeed Awan Dept.of SE FUIEMS Pakistan Dept.of CE College of E & ME NUST Pakistan Dept.of CS CUT Abbottabad Pakistan Dept.of CE College of E & ME NUST Pakistan

The inventions of modern scientific applications of recent era have introduced many new dimensions of the computing technology. Conventionally two basic types of the computing technologies have ever been in use including the computing based on the extremely high speed application specific integrated circuits (ASICs) and the computing based on the most flexible programmable general purpose processors (GPPs). So far these domains of computing have been targeting the two different types of the applications including the high speed applications with the use of the ASICs and versatile programmable applications with the use of the GPPs. But the recent scientific research has introduced many new application areas which are requiring both the high speed as well as flexibility of the computing platforms. In order to fulfill these requirements of such type of applications, the reconfigurable computing technology has been introduced. reconfigurable computing is intended to fill the gape between the ASICs and GPPs by integrating the both technologies on a single chip. This research paper introduces the role of reconfigurable computing in the execution of such a type of newly born modern scientific applications.

关键词： reconfigurable computing ASICs fpgas Configuration Bits/reams reconfigurable Units

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Network Processing in Multi-core fpgas with Integrated Cache-Network Interface

Network Processing in Multi-core FPGAs with Integrated Cache...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Christoforos Kachris George Nikiforos Stamatis Kavadias Vassilis Papaefstathiou Manolis Katevenis Institute of Computer Science Foundation for Research and Technology Hellas Crete Greece

Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architectures become more distributed. A multicore FPGA platform with cache-integrated network interfaces (NIs) is presented, appropriate for scalable multicores, that combine the best of two worlds -the flexibility of caches (using implicit communication) and the efficiency of scratchpad memories (using explicit communication): on-chip SRAM is configurable shared among caching, scratchpad, and virtualized NI functions. The proposed system has been implemented in a four-core FPGA. Special hardware primitives (counter, queues) are used for the the communication and synchronization of the cores that are most suitable in network processing applications. The paper presents the performance evaluation of the proposed system in the domain of network processing. Two representatives benchmarks are used, one for header processing and one for payload processing. The system is evaluated in terms of performance and the communication overhead is measured. Furthermore, two approaches for the communication of the processors are evaluated and compared, common queue and distributed queues.

关键词： Program processors Radiation detectors Nickel Field programmable gate arrays Synchronization Hardware

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Power Characterisation for Fine-Grain reconfigurable Fabrics

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INTERNATIONAL JOURNAL OF reconfigurable computing 2010年第1期2010卷

作者： Becker, Tobias Jamieson, Peter Luk, Wayne Cheung, Peter Y. K. Rissa, Tero Imperial Coll London Dept Comp London SW7 2AZ England Imperial Coll London Dept EEE London SW7 2AZ England Nokia Devices R&D Tampere Finland

This paper proposes a benchmarking methodology for characterising the power consumption of the fine-grain fabric in reconfigurable architectures. This methodology is part of the GroundHog 2009 power benchmarking suite. It covers active and inactive power as well as advanced low-power modes. A method based on random number generators is adopted for comparing activity modes. We illustrate our approach using five field-programmable gate arrays (fpgas) that span a range of process technologies: Xilinx Virtex-ii Pro, Spartan-3E, Spartan-3AN, Virtex-5, and Silicon Blue iCE65. We find that, despite improvements through process technology and low-power modes, current devices need further improvements to be sufficiently power efficient for mobile applications. The Silicon Blue device demonstrates that performance can be traded off to achieve lower leakage.

关键词： reconfigurable architectures

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Comparing performance and energy efficiency of fpgas and GPUs for high productivity computing

Comparing performance and energy efficiency of FPGAs and GPU...

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IEEE International conference on Field-Programmable technology (FPT)

作者： Brahim Betkaoui David B. Thomas Wayne Luk Department of Computing Imperial College London London UK

This paper provides the first comparison of performance and energy efficiency of high productivity computing systems based on FPGA (Field-Programmable Gate Array) and GPU (Graphics Processing Unit) technologies. The search for higher performance compute solutions has recently led to great interest in heterogeneous systems containing FPGA and GPU accelerators. While these accelerators can provide significant performance improvements, they can also require much more design effort than a pure software solution, reducing programmer productivity. The CUDA system has provided a high productivity approach for programming GPUs. This paper evaluates the High-Productivity reconfigurable Computer (HPRC) approach to FPGA programming, where a commodity CPU instruction set architecture is augmented with instructions which execute on a specialised FPGA co-processor, allowing the CPU and FPGA to co-operate closely while providing a programming model similar to that of traditional software. To compare the GPU and FPGA approaches, we select a set of established benchmarks with different memory access characteristics, and compare their performance and energy efficiency on an FPGA-based Hybrid-Core system with a GPU-based system. Our results show that while GPUs excel at streaming applications, high-productivity reconfigurable computing systems outperform GPUs in applications with poor locality characteristics and low memory bandwidth requirements.

关键词： Benchmark testing Field programmable gate arrays Coprocessors Graphics processing unit Programming Kernel Instruction sets

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SeqHive: A reconfigurable Computer Cluster for Genome Re-sequencing

SeqHive: A Reconfigurable Computer Cluster for Genome Re-seq...

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International conference on Field Programmable Logic and applications

作者： Kristian Stevens Henry Chen Terry Filiba Peter McMahon Yun S. Song Department of Computer Science University of California Davis Davis CA USA Berkeley Wireless Research Center Berkeley CA USA Department of Electrical Engineering University of Stanford Stanford CA USA Department of Electrical Engineering and Computer Sciences University of California Berkeley Berkeley CA USA

We demonstrate how Field Programmable Gate Arrays (fpgas) may be used to address the computing challenges associated with assembling genome sequences from recent ultra-high-throughput sequencing technologies. Advances in sequencing technology allow researchers to generate immense amounts of raw data in the form of short reads with high error rates. A prerequisite to effectively utilizing this data for most applications is accurate alignment to a reference genome. While dynamic programming (DP) alignment algorithms are generally avoided on conventional architectures due to their computational complexity, they can be tailored for efficient implementation on systolic architectures. We describe and implement the first system capable of assembling large genomes using DP. We implemented application-specific DP algorithms for aligning data from ultra-high-throughput sequencers in a reconfigurable computing cluster. To obtain the necessary throughput while maintaining scoring integrity, we extended the compact encoding scheme of Lipton and Lopresti for our application. Each FPGA is capable of rapidly aligning multiple reads in parallel against a long reference genome. The reconfigurable cluster proves to be scalable and capable of processing real world datasets with a sustained performance of 11 tera cell updates per second. We examine the advantages and practicality of our system by benchmarking real genomic data from a large sequencing project. Our exhaustive validation confirms that application specific computing hardware can provide more accurate results than current heuristic methods and remain practical. While directly addressing the important problem of genomic assembly, particularly in circumstances where error rates or evolutionary divergence is high, the methods presented are also relevant to many other current applications for this type of data.

关键词： Field programmable gate arrays Genomics Bioinformatics Computer architecture Random access memory Encoding Parallel processing

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Non-Instruction Fetch-Based Architecture Reduces Almost 100 Percent of the Dynamic Power and Energy

Non-Instruction Fetch-Based Architecture Reduces Almost 100 ...

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IEEE/ACM Int'l conference on & Int'l conference on Cyber, Physical and Social computing (CPSCom) Green computing and Communications (GreenCom)

作者： Abdelghani Renbi Lennart Lindh Jerker Delsing Eislab Luleå University of Technology Sweden Embedded Systems Department Jönköping University Sweden

This paper demonstrates the benefit of fpgas for better power and energy efficiency when exploited for non-instruction fetch-based architecture. By replacing load/store architecture by non-instruction fetch-based designs for matrix multiplication, we reduced almost 100 percent of the dynamic power. Hence reconfigurable computing is the potential key to saving energy in battery-powered embedded systems and to solve the dissipated power dilemma, as the heat becomes the bottleneck of traditional high frequency processors. If the same strategy is applied to mainstream computers and data center servers, we will not only reduce electricity bills but we will also contribute to greener computing by improving the IT sector's CO2 emissions. The work involves three different designs, which multiply two matrices A and B of nxn 32-bit items and store the result in C matrix of nxn 64-bit items. The first two designs employ a single-purpose processor with different number of storage registers 2n and 2n 2 and the third design uses a computer system piloted by NIOS ii/e processor with on-chip memory. The designs were captured in VHDL language and prototyped on an Alter a Cyclone ii EP2C35F672C6 device. Both synthesis and place&route steps were performed with Quart us ii 6.0 Web Edition. The experiments were made on Altera DE2 board. In this paper we have also clarified further the power estimation error of Alter a power estimation tools, which we have evaluated in.

关键词： Computer architecture Field programmable gate arrays Clocks Transmission line matrix methods Estimation error Embedded systems Power demand

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Virtualization of computing Resources in RCS for Multi-Task Stream applications

Virtualization of Computing Resources in RCS for Multi-Task ...

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International conference on reconfigurable computing and fpgas

作者： Kirischian, L. Dumitriu, V. Chun, P. W. Ryerson Univ Dept Elect & Comp Engn Toronto ON Canada MDA Space Miss Brampton ON Canada

ISBN: (纸本)9781424452934

The possibility for distribution of FPGA resources in the temporal domain for multi-modal & multi-task workloads conceptually allows virtualization of logic, communication and input/output resources similar to memory virtualization in advanced conventional computers (e.g. superscalar). This, in turn, can dramatically increase the cost-effectiveness of FPGA based reconfigurable computing Systems (RCS). In the presented "proof-of-concept" research the following topics have been investigated, developed and tested: i) architecture of a platform to support the dynamic allocation of Application Specific Virtual Processors (ASVP), ii) mechanisms for run-time on-chip assembly of ASVP from Virtual Hardware Components (VHC) and iii) mechanisms for run-time on-chip components (VHC) relocation in predetermined regions of the FPGA device. The above mechanisms have been implemented and tested on a specially developed platform: the Multi-task Adaptive reconfigurable System (MARS) Platform. The actual application of MARS was prototyping a high-performance multi-mode stereo-vision system (200 fps) for the next generation of space-borne computing platforms.

关键词： Run-time reconfiguration (RTR) reconfigurable systems Resources virtualization FPGA Virtual processor Virtual component component relocation on-chip assembly

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Design of reconfigurable UWB transmitter to implement multi-rate MB-OFDM UWB wireless system

Design of reconfigurable UWB transmitter to implement multi-...

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International conference on Advances in computing, Control and Telecommunication Technologies, ACT 2009

作者： Vennila, C. Lakshminarayanan, G. Tungala, Sowjanya Department of ECE.NITT National Institute of Technology Tiruchirappalli Tamilnadu India

ISBN: (纸本)9780769539157

Dynamic and partial reconfiguration allows efficient resource exploitation by configuring tasks on demand and may lead to a decreased chip size, which reduces the static power consumption and can be used in adaptive systems. These systems are able to adapt themselves to the demand of their environment during run-time. The benefit of using dynamic reconfiguration is the possibility to use smaller fpgas by outsourcing configuration data. This flexibility can be used for many wireless applications. In this paper, a novel Ultra Wide Band (UWB) transmitter is reconfigured to implement multirate MB-OFDM UWB wireless system. In order to prove the efficacy of this approach, a UWB transmitter was designed with a reprogrammable puncturer supporting seven different data rates to demonstrate the practical use of partial reconfiguration technology. The dynamic reconfigurable UWB transmitter proposed in this paper consumes comparatively minimum FPGA resources than the conventional static reconfiguration. Reconfiguration latency is also minimum since the dynamic reconfigurable module taken in this work consumes only 15 slices and successfully implemented on XILINX Virtex ii Pro XC2VP30. © 2009 IEEE.

关键词： Field programmable gate arrays (FPGA)

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PROTOFLEX: Towards Scalable, Full-System Multiprocessor Simulations Using fpgas

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ACM TRANSACTIONS ON reconfigurable technology AND SYSTEMS 2009年第2期2卷 1–32页

作者： Chung, Eric S. Papamichael, Michael K. Nurvitadhi, Eriko Hoe, James C. Mai, Ken Falsafi, Babak Comp Architecture Lab Carnegie Mellon Pittsburgh PA 15213 USA Ecole Polytech Fed Lausanne Parallel Syst Architecture Lab Lausanne Switzerland

Functional full-system simulators are powerful and versatile research tools for accelerating architectural exploration and advanced software development. Their main shortcoming is limited throughput when simulating large multiprocessor systems with hundreds or thousands of processors or when instrumentation is introduced. We propose the PROTOFLEX simulation architecture, which uses fpgas to accelerate full-system multiprocessor simulation and to facilitate high-performance instrumentation. Prior FPGA approaches that prototype a complete system in hardware are either too complex when scaling to large-scale configurations or require significant effort to provide full-system support. In contrast, PROTOFLEX virtualizes the execution of many logical processors onto a consolidated number of multiple-context execution engines on the FPGA. Through virtualization, the number of engines can be judiciously scaled, as needed, to deliver on necessary simulation performance at a large savings in complexity. Further, to achieve low-complexity full-system support, a hybrid simulation technique called transplanting allows implementing in the FPGA only the frequently encountered behaviors, while a software simulator preserves the abstraction of a complete system. We have created a first instance of the PROTOFLEX simulation architecture, which is an FPGA-based, full-system functional simulator for a 16-way UltraSPARC iiI symmetric multiprocessor server, hosted on a single Xilinx Virtex-ii XCV2P70 FPGA. On average, the simulator achieves a 38x speedup (and as high as 49x) over comparable software simulation across a suite of applications, including OLTP on a commercial database server. We also demonstrate the advantages of minimal-overhead FPGA-accelerated instrumentation through a CMP cache simulation technique that runs orders-of-magnitude faster than software.

关键词： Design Experimentation Performance FPGA simulator emulator prototype multicore multiprocessor

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POWER CHARACTERISATION FOR THE FABRIC IN FINE-GRAIN reconfigurable ARCHITECTURES

POWER CHARACTERISATION FOR THE FABRIC IN FINE-GRAIN RECONFIG...

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5th Southern conference on Programmable Logic

作者： Becker, Tobias Jamieson, Peter Luk, Wayne Cheung, Peter Y. K. Rissa, Tero Imperial Coll London Dept Comp London England Imperial Coll London Dept EEE London England Nokia Devices R&D Espoo Finland

ISBN: (纸本)9781424438464

This paper proposes a methodology for characterising power consumption of the fine-grain fabric in reconfigurable architectures. It covers active and inactive power as well as advanced low-power modes. A method based on random number generators is adopted for comparing activity modes. We illustrate our approach using four field-programmable gate arrays (fpgas) that span a range of process technologies: Virtex-ii Pro, Spartan-3E, Spartan-3AN, and Virtex-5. We find that, despite improvements through process technology and low-power modes, current devices need further improvements to be sufficiently power efficient for mobile applications.

关键词： reconfigurable architectures

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