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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

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Research and design of on-board dynamic reconfigurable router

Research and design of on-board dynamic reconfigurable route...

引用

NCM 2009 - 5th International Joint conference on Int. Conf. on Networked computing, Int. Conf. on Advanced Information Management and Service, and Int. Conf. on Digital Content, Multimedia technology and its applications

作者： Mao, Chunjing Guan, Yong Jungwirth, David Capital Normal University Beijing China Vienna University of Technology Vienna Austria

ISBN: (纸本)9780769537696

In order to satisfy the requirement of aerocraft's multi- transmission for further development, the paper leads to a resolution about on-board dynamic reconfigurable Spacewire routing technology. Based on the network level analysis of Spacewire standard, it built the architecture of router with wormhole routing theory. A simulation model of router had been set to verify the design, and braking-problem from wormhole routing-blocking had been solved with BWR. And a prototype of dynamic reconfigurable router had been built by using the characteristic of high-speed processing and dynamic reconfiguration of fpgas. © 2009 IEEE.

关键词： Dynamic models

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FPGA Implementation of a Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier

FPGA Implementation of a Decimal Floating-Point Accurate Sca...

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： Malte Baesler Thomas Teufel Institute for Reliable Computing Hamburg University of Technology Hamburg Germany

Decimal floating point (DFP) operations are very important for applications, that cannot tolerate errors from conversions between binary and decimal formats, for instance scientific, commercial, financial and internet-based applications. In this paper we present a parallel decimal fixed-point multiplier, designed to exploit the features of fpgas. Our multiplier is based on BCD recoding schemes, fast partial product generation and a BCD-4221 carry save adder reduction tree. Furthermore, we extend the multiplier with an accurate scalar product unit in order to provide an important operation with smallest possible rounding error as proposed in. Finally the design is implemented and tested on a Xilinx Virtex-ii Pro FPGA platform.

关键词： Field programmable gate arrays Floating-point arithmetic Application specific processors Concurrent computing Testing Internet Roundoff errors Hardware Prototypes CMOS logic circuits

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Effects of Simplistic Online Synthesis for AMIDAR Processors

Effects of Simplistic Online Synthesis for AMIDAR Processors

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： Stefan Döbrich Christian Hochberger Embedded Systems Dresden University of Technology Dresden Germany

Future chip technologies will change the way we deal with hardware design. (1) logic resources will be available in vast amount and (2) engineering specialized designs for particular applications will no longer be the general approach as the non recurring expenses will grow tremendously. Thus, we believe that online synthesis that takes place during the execution of an application is one way to overcome these problems. In this paper we show that even a relative simplistic synthesis approach can have a strong impact on the performance of compute intensive applications.

关键词： reconfigurable logic Field programmable gate arrays Logic design Circuit synthesis Embedded system Hardware Runtime Acceleration High level languages Computer architecture

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Design of Coarse-Grained Dynamically reconfigurable Architecture for DSP applications

Design of Coarse-Grained Dynamically Reconfigurable Architec...

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： Chenxin Zhang Thomas Lenart Henrik Svensson Viktor Öwall Department of Electrical and Information Technology Lund University Lund Sweden

This paper presents the design and implementation of a coarse-grained reconfigurable architecture, targeting digital signal processing applications. The proposed architecture is constructed from a mesh of resource cells, containing separated processing and memory elements that communicate via a hybrid interconnect network. Parameterizable design of resource cells enables flexible mapping of arbitrary applications at system compile-time, and the feature of dynamic reconfigurability provides mapping possibilities during system run-time to adapt to the current operational and processing conditions. Functionality and flexibility of the proposed architecture is demonstrated through mapping of a radix-22 FFT processor reconfigurable between 32 and 1024 points. Performance evaluation exhibits a great reconfigurability and execution time reduction when compared to a traditional DSP and ARM solution.

关键词： reconfigurable architectures Digital signal processing Hardware Computer architecture Field programmable gate arrays Routing Signal design Signal processing algorithms Resource management Logic arrays

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Symmetric Multiprocessor Systems on FPGA

Symmetric Multiprocessor Systems on FPGA

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： Pablo Huerta Javier Castillo Cesar Pedraza Javier Cano Jose Ignacio Martinez Department of Computer Architecture and Technology Computer Science and IA Rey Juan Carlos University Mostoles Spain

Advances in FPGA technologies allow designing highly complex systems using on-chip FPGA resources and intellectual property (IP) cores. Furthermore, it is possible to build multiprocessor systems using hard-core or soft-core processors, increasing the range of applications that can be implemented on an FPGA. In this paper we propose a symmetric multiprocessor architecture using the Microblace soft-core processor, and the operating system support needed for running multithreaded applications. Four systems with different shared memory configurations have been implemented on FPGA and tested with parallel applications to show its performance.

关键词： Multiprocessing systems Field programmable gate arrays Operating systems Computer architecture Computer science System-on-a-chip Intellectual property Application software System testing Taxonomy

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Virtualization of computing Resources in RCS for Multi-task Stream applications

Virtualization of Computing Resources in RCS for Multi-task ...

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： L. Kirischian V. Dumitriu P. W. Chun Department of Electrical and Computer Engineering Ryerson University Toronto Canada MDA Space Missions Brampton Canada

The possibility for distribution of FPGA resources in the temporal domain for multi-modal & multi-task workloads conceptually allows virtualization of logic, communication and input/output resources similar to memory virtualization in advanced conventional computers (e.g. superscalar). This, in turn, can dramatically increase the cost-effectiveness of FPGA based reconfigurable computing systems (RCS). In the presented ¿proof-of-concept¿ research the following topics have been investigated, developed and tested: i) architecture of a platform to support the dynamic allocation of application specific virtual processors (ASVP), ii) mechanisms for run-time on-chip assembly of ASVP from virtual hardware components (VHC) and iii) mechanisms for run-time on-chip components (VHC) relocation in predetermined regions of the FPGA device. The above mechanisms have been implemented and tested on a specially developed platform: the multi-task adaptive reconfigurable system (MARS) platform. The actual application of MARS was prototyping a high-performance multi-mode stereo-vision system (200 fps) for the next generation of space-borne computing platforms.

关键词： Application virtualization Resource virtualization Field programmable gate arrays Application software Runtime Mars reconfigurable logic Distributed computing Testing Computer architecture

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Scheduling and 2D placement heuristics for partially reconfigurable systems

Scheduling and 2D placement heuristics for partially reconfi...

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2009 International conference on Field-Programmable technology, FPT'09

作者： Redaelli, F. Santambrogio, M.D. Rana, V. Memik, S. Ogrenci Dipartimento di Elettronica e dell'Informazione Politecnico di Milano Milano 20133 Italy Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology Cambridge MA 02139 United States Department of Electrical Engineering and Computer Science Northwestern University Evanston IL 60208 United States

ISBN: (纸本)9781424443772

This paper proposes new scheduling and 2D placement heuristics for partially dynamically reconfigurable systems. One specific focus of this work is to deal with applications containing hundreds of tasks grouped in a few number of task types. Such a task graph structure is representative of data intensive high performance applications. We present three variations to our task management method that correspond to three possible system scenarios: (i) possessing complete static knowledge of task sequences, (ii) only having information on the maximum resource requirement by any task expected to be executed, and (iii) having no prior knowledge of any kind about the workload. Each variant of our scheduler addresses an architecture that best matches the needs of a particular configuration of the system. Together they form a complete set of techniques to serve partial dynamic reconfiguration of massively parallel computing systems. © 2009 IEEE.

关键词： Scheduling

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A Dynamically reconfigurable Platform for Fixed-Point FIR Filters

A Dynamically Reconfigurable Platform for Fixed-Point FIR Fi...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Daniel Llamocca Marios Pattichis G. Alonzo Vera Electrical and Computer Engineering Department University of New Mexico Albuquerque NM USA Microelectronics Research and Development Corporation Albuquerque NM USA

Many DSP, image and video processing applications use finite impulse response (FIR) filters as basic computing blocks. Our paper introduces an efficient dynamically reconfigurable FIR system that can adapt the number of filter coefficients, and their values, in real time. Here, dynamic reconfiguration is used to switch between different, pre-computed, fixed-point realizations of different digital filters. Our platform relies on the use of distributed arithmetic blocks, mapped to the specific LUTs of the underlying FPGA. Dynamic reconfiguration of the coefficients is limited to changing a small number of relevant LUT contents, while leaving the rest of the architecture intact. We investigate the dynamic system throughput as a function of the dynamic reconfiguration rate.

关键词： Finite impulse response filter Field programmable gate arrays Arithmetic Table lookup Switches Digital filters Throughput Hardware CMOS technology Digital signal processing

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A reconfigurable Design Framework for FPGA Adaptive computing

A Reconfigurable Design Framework for FPGA Adaptive Computin...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Ming Liu Zhonghai Lu Wolfgang Kuehn Shuo Yang Axel Jantsch Physics Institute Justus Liebig University Giessen Germany Department of Electronic Computer and Software Systems Royal Institute of Technology Sweden

Partial reconfiguration (PR) offers the possibility to adaptively change part of the FPGA design without stopping the remaining system. In this paper, we present a comprehensive framework for adaptive computing, in which design key points of hardware processes, system interconnections, operating systems (OS), device drivers, scheduler software as well as context switching are respectively concerned in different hardware/software layers. A case study is discussed to demonstrate an example of swapping a Flash memory controller and an SRAM controller in response to diverse memory access needs. Result analysis reveals a more efficient resource utilization of 52.1% I/O pads, 86.5% LUTs and 81.3% Flip-Flops, when compared to the static design with same functionalities. A small reconfiguration overhead of context switching is measured within the range from hundreds of microseconds to milliseconds. Moreover, technical perspectives are analyzed and it is foreseen to obtain great benefits with the proposed design framework in object applications of particle physics experiments.

关键词： Field programmable gate arrays Hardware Processor scheduling Resource management Physics computing Kernel Flash memory Random access memory Application software Linux

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On the Implementation of Central Pattern Generators for Periodic Rhythmic Locomotion

On the Implementation of Central Pattern Generators for Peri...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Cesar Torres-Huitzil Information Technology Laboratory (LTI) CINVESTAV Tamaulipas Mexico

This paper presents the feasibility study of the efficient digital hardware implementation of a neural model to generate locomotion patterns of periodic rhythmic movements inspired by biological neural networks found in animal nervous system called Central Pattern Generators (CPGs). The proposed implementation contains a dedicated digital module that mimics the functionality and organization of the fundamental Amari-Hopfield CPG. This module is attached to an embedded processor running the uclinux operating system. The present paper deals only with the implementation of the basic CPG component and how to embed it under a System on a Chip (SoC) approach in order to be controlled by external commands in a high level transparent way for application development. The system is implemented on a Field Programmable Gate Array (FPGA) device providing a compact, flexible and expandable solution for generating periodic rhythmic patterns in robot control applications. According to experimental results, the architecture can be used as a basis for a biomimetic intelligent embedded control platform for articulated autonomous robots.

关键词： Field programmable gate arrays Intelligent robots Neural network hardware Biological system modeling Biological neural networks Animals Nervous system Operating systems System-on-a-chip Control systems

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