检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

408 篇 会议
9 篇 期刊文献
1 篇 学位论文

馆藏范围

418 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

221 篇 工学
- 210 篇 计算机科学与技术...
- 100 篇 软件工程
- 49 篇 电气工程
- 49 篇 电子科学与技术（可...
- 22 篇 控制科学与工程
- 17 篇 信息与通信工程
- 12 篇 动力工程及工程热...
- 7 篇 土木工程
- 5 篇 光学工程
- 5 篇 建筑学
- 5 篇 航空宇航科学与技...
- 5 篇 生物工程
- 4 篇 机械工程
- 4 篇 环境科学与工程（可...
- 3 篇 仪器科学与技术
- 2 篇 生物医学工程（可授...
66 篇 理学
- 39 篇 数学
- 17 篇 物理学
- 6 篇 生物学
- 6 篇 系统科学
- 4 篇 统计学（可授理学、...
- 2 篇 化学
- 1 篇 地球物理学
- 1 篇 地质学
13 篇 管理学
- 13 篇 管理科学与工程(可...
- 9 篇 工商管理
3 篇 经济学
- 3 篇 应用经济学
3 篇 医学
- 3 篇 临床医学
2 篇 教育学
- 2 篇 教育学
1 篇 法学
- 1 篇 社会学

主题

149 篇 field programmab...
96 篇 hardware
69 篇 computer archite...
35 篇 field programmab...
32 篇 application soft...
32 篇 fpga
24 篇 reconfigurable a...
20 篇 runtime
20 篇 acceleration
19 篇 parallel process...
19 篇 reconfigurable c...
16 篇 routing
16 篇 digital signal p...
15 篇 high performance...
14 篇 concurrent compu...
14 篇 reconfigurable l...
14 篇 random access me...
14 篇 clocks
12 篇 bandwidth
12 篇 microprocessors

机构

7 篇 department of co...
5 篇 george washingto...
4 篇 institute for re...
3 篇 rochester instit...
3 篇 george mason uni...
3 篇 karlsruhe instit...
3 篇 xilinx inc san j...
2 篇 heinz nixdorf in...
2 篇 chengdu universi...
2 篇 northeastern uni...
2 篇 brocade communic...
2 篇 department of el...
2 篇 institute of com...
2 篇 embedded softwar...
2 篇 department of el...
2 篇 variel microelec...
2 篇 institut für tec...
2 篇 institute for se...
2 篇 faculty of elect...
2 篇 department of el...

作者

9 篇 luk wayne
6 篇 wayne luk
4 篇 cheung peter y. ...
4 篇 axel jantsch
4 篇 zhonghai lu
4 篇 t. el-ghazawi
4 篇 ming liu
4 篇 peter y. k. cheu...
4 篇 wolfgang kuehn
3 篇 s.j. visser
3 篇 david kearney
3 篇 sonia lopez
3 篇 a.s. dawood
3 篇 j.a. williams
3 篇 john wawrzynek
3 篇 e. el-araby
3 篇 sven-ole voigt
3 篇 shaoyi cheng
3 篇 w. luk
3 篇 prasanna viktor ...

语言

411 篇 英文
7 篇 其他

检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

共 418 条记录，以下是221-230 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Design of reconfigurable UWB Transmitter to Implement Multi-rate MB-OFDM UWB Wireless System

Design of Reconfigurable UWB Transmitter to Implement Multi-...

引用

International conference on Advances in computing, Control, & Telecommunication Technologies (ACT)

作者： C. Vennila G. Lakshminarayanan Sowjanya Tungala Department of ECE NITT National Institute of Technology Tiruchirappalli Tamil Nadu India

Abstract-Dynamic and partial reconfiguration allows efficient resource exploitation by configuring tasks on demand and may lead to a decreased chip size, which reduces the static power consumption and can be used in adaptive systems. These systems are able to adapt themselves to the demand of their environment during run-time. The benefit of using dynamic reconfiguration is the possibility to use smaller fpgas by outsourcing configuration data. This flexibility can be used for many wireless applications. In this paper, a novel Ultra Wide Band (UWB) transmitter is reconfigured to implement multirate MB-OFDM UWB wireless system. In order to prove the efficacy of this approach, a UWB transmitter was designed with a reprogrammable puncturer supporting seven different data rates to demonstrate the practical use of partial reconfiguration technology. The dynamic reconfigurable UWB transmitter proposed in this paper consumes comparatively minimum FPGA resources than the conventional static reconfiguration. Reconfiguration latency is also minimum since the dynamic reconfigurable module taken in this work consumes only 15 slices and successfully implemented on XILINX Virtex ii Pro XC2VP30.

关键词： Transmitters Field programmable gate arrays Runtime Bandwidth Proposals Energy consumption Ultra wideband technology FCC OFDM modulation Telecommunication computing

来源：评论

学校读者我要写书评

暂无评论

Power characterisation for the fabric in fine-grain reconfiguralbe architectures

Power characterisation for the fabric in fine-grain reconfig...

引用

Southern conference on Programmable Logic

作者： Tobias Becker Peter Jamieson Wayne Luk Peter Y. K. Cheung Tero Rissa Department of Computing Imperial College London UK Department of EEE Imperial College London UK Nokia Devices Research and Development Finland

This paper proposes a methodology for characterising power consumption of the fine-grain fabric in reconfigurable architectures. It covers active and inactive power as well as advanced low-power modes. A method based on random number generators is adopted for comparing activity modes. We illustrate our approach using four field-programmable gate arrays (fpgas) that span a range of process technologies: Virtex-ii Pro, Spartan-3E, Spartan-3AN, and Virtex-5. We find that, despite improvements through process technology and low-power modes, current devices need further improvements to be sufficiently power efficient for mobile applications.

关键词： Fabrics Field programmable gate arrays Energy consumption Testing Circuits reconfigurable architectures Power measurement Ring oscillators Educational institutions Temperature dependence

来源：评论

学校读者我要写书评

暂无评论

Exploring the evolution of NoC-based Spiking Neural Networks on fpgas

Exploring the evolution of NoC-based Spiking Neural Networks...

引用

IEEE International conference on Field-Programmable technology (FPT)

作者： F Morgan S Cawley B Mc Ginley S Pande LJ Mc Daid B Glackin J Maher J Harkin Bio-Inspired Electronics and Reconfigurable Computing Research Group National University of Ireland Galway Ireland Bio-Inspired Electronics and Reconfigurable Computing Research Group (BIRC) National University of Ireland Galway Intelligent Systems Research Centre University of Ulster Londonderr UK Intelligent Systems Research Centre Magee Campus Derry Northern Ireland

Bio-inspired paradigms such as spiking neural networks (SNNs) offer the potential to emulate the repairing and adaptive ability of the brain. This paper presents EMBRACE-FPGA, a scalable, configurable network on chip (NoC)-based SNN architecture, implemented on Xilinx Virtex ii-Pro FPGA hardware. In association with a genetic algorithm-based hardware evolution platform, EMBRACE-FPGA provides a computing platform for intrinsic hardware evolution, which can be used to explore the evolution and adaptive capabilities of hardware SNNs. Results demonstrate the application of the hardware SNN evolution platform to solve the XOR benchmark problem.

关键词： Neural networks Field programmable gate arrays Neurons Evolution (biology) Computer architecture Biological neural networks Network-on-a-chip Neural network hardware Biology computing Power engineering computing

来源：评论

学校读者我要写书评

暂无评论

An on Chip Network inside a FPGA for Run-Time reconfigurable Low Latency Grid Communication

An on Chip Network inside a FPGA for Run-Time Reconfigurable...

引用

Euromicro Symposium on Digital System Design

作者： Jochen Strunk Toni Volkmer Wolfgang Rehm Heiko Schick Computer Architecture Group Chemnitz University of Technology Germany IBM Deutschland Research and Development GmbH Germany

In this paper a low latency, on chip communication network (NoC) for a run-time reconfigurable (RTR) grid inside dynamically and partially reconfigurable (DPR) fpgas is proposed, which supports the arbitrary placement of run-time reconfigurable modules (RTRM) inside the grid. The dedicated, fully meshed, silicon network should support the arrangement of communication channels between the RTRMs within the different partially reconfigurable regions (PRRs) on the FPGA. The design of the network guarantees a low latency communication of RTRMs without mutual interference of each other. In comparison with an implementation using FPGA resources the dedicated silicon network could save an huge amount of resources in terms of transistors. The new degree of parallel communication provided for a RTR grid with arbitrarily placeable RTRMs offers new application fields for DPR capable fpgas. Multiple user applications with inter-communicating offload compute kernels can be loaded on a host coupled FPGA accelerator, a real-time (RT) system with concurrent communication tasks are possible and enhancing the functionality on demand for embedded systems is conceivable. A case study was conducted for proof of concept and for the verification of the run-time environment system, which manages the configurable network.

关键词： Network-on-a-chip Field programmable gate arrays Runtime Delay Silicon Communication networks Communication channels Interference Concurrent computing Embedded computing

来源：评论

学校读者我要写书评

暂无评论

High computing-intensive array system design and hardware implement

High computing-intensive array system design and hardware im...

引用

International conference on ASIC

作者： Yu-kun Song Xiao-lei Wang Wei Ni Duo-li Zhang Gao-ming Du Institute of VLSI Design Hefei University of Technology Hefei China

This paper addresses a novel coarse grain dynamic reconfigurable computing system, called DReAC-2, design and hardware implement. A whole DReAC-2 system integrates a Nios ii processor, which manages the whole reconfigurable system, and a dynamic reconfigurable coprocessor, which comprises of an 8x8 processing node array designed for high regularity, high computation-intensive tasks. Hardware prototype of DReAC-2 has been implemented on the ALTERA STRATIX ii EP2S180 development board. According to task's nature, MIMD computing array can select either parallel-pipelined pattern or array-parallel pattern to gain the better performance. The experiment results show that DReAC-2 achieves much higher 10~100x factor than NIOS ii processors, and 2x~4x factors and higher precision than some others reconfigurable processors.

关键词： Hardware Concurrent computing Delta modulation Coprocessors Prototypes Application specific integrated circuits Computer architecture Computer applications High performance computing Adaptive arrays

来源：评论

学校读者我要写书评

暂无评论

reconfigurable sparse/dense matrix-vector multiplier

Reconfigurable sparse/dense matrix-vector multiplier

引用

IEEE International conference on Field-Programmable technology (FPT)

作者： Georgi Kuzmanov Mottaqiallah Taouil Computer Engineering Laboratory EEMCS Delft University of Technnology Delft Netherlands

We propose an ANSI/IEEE-754 double precision floating-point matrix-vector multiplier. Its main feature is the capability to process efficiently both dense matrix-vector multiplications (DMVM) and sparse matrix-vector multiplications (SMVM). The design is composed of multiple processing elements (PE) and is optimized for fpgas. We investigate theoretically the boundary conditions when the DMVM equals the SMVM performance with respect to the matrix sparsity. Thus, we can determine the most efficient processing mode configuration with respect to the input data sparsity. Furthermore, we evaluate our design both with simulations and on real hardware. We experimented on an Altix 450 machine using the SGI reconfigurable application specific computing (RASC) services, which couple dual-core Itanium-2 processors with Virtex-4 LX200 fpgas. Our design has been routed and executed on the Altix 450 machine at 100 MHz. Experimental results suggest that only two PEs suffice to outperform the pure software SMVM execution. The performance improvement at the kernel level scales near linearly to the number of configured PEs both for the SMVM and DMVM. Compared to related work, the design does not indicate any performance degradation and performs equally or better than designs optimized either for SMVM or DMVM alone.

关键词： Sparse matrices Design optimization Field programmable gate arrays Boundary conditions Computational modeling Hardware Application software Computer applications Kernel Degradation

来源：评论

学校读者我要写书评

暂无评论

Scheduling and 2D placement heuristics for partially reconfigurable systems

Scheduling and 2D placement heuristics for partially reconfi...

引用

IEEE International conference on Field-Programmable technology (FPT)

作者： F. Redaelli M.D. Santambrogio V. Rana S. Ogrenci Memik Dipartimento di Elettronica e dellInformazione Politecnico di Milano Milan Italy Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology Cambridge MA USA Department of Electrical Engineering and Computer Science Northwestern University Evanston IL USA

This paper proposes new scheduling and 2D placement heuristics for partially dynamically reconfigurable systems. One specific focus of this work is to deal with applications containing hundreds of tasks grouped in a few number of task types. Such a task graph structure is representative of data intensive high performance applications. We present three variations to our task management method that correspond to three possible system scenarios: (i) possessing complete static knowledge of task sequences, (ii) only having information on the maximum resource requirement by any task expected to be executed, and (iii) having no prior knowledge of any kind about the workload. Each variant of our scheduler addresses an architecture that best matches the needs of a particular configuration of the system. Together they form a complete set of techniques to serve partial dynamic reconfiguration of massively parallel computing systems.

关键词： Processor scheduling Dynamic scheduling Application software Knowledge management Resource management Computer architecture High performance computing Supercomputers Prefetching Computer science

来源：评论

学校读者我要写书评

暂无评论

Implementation of reconfigurable Adaptive Filtering Algorithms

Implementation of Reconfigurable Adaptive Filtering Algorith...

引用

International conference on Signal Processing Systems, ICSPS

作者： Srinivasa Chaitanya K. P. Muralidhar C.B. Rama Rao National Institute of Technology Calicut Calicut Kerala IN National Institute of Technology Warangal India

Filtering data in real-time requires dedicated hardware to meet demanding time requirements. If the statistics of the signal are not known, then adaptive filtering algorithms can be implemented to estimate the signals statistics iteratively. Modern field programmable gate arrays (fpgas) include the resources needed to design efficient filtering structures. This paper aims to combine efficient filter structures with optimized code to create a system-on-programmable-chip (SoPC) solution for various adaptive filtering problems. The algorithms in this paper are implemented using the Cyclone ii FPGA device chipped on Altera DE2 board. The inbuilt NIOS ii soft core processor of the FPGA device acts as the processor for processing applications. In this paper least mean square (LMS) adaptive filtering algorithm and its variations have been implemented in software and as well as hardware/software co-design for the NIOS ii processor. A comparison is then made between the software implementation and hardware/software co-design implementation. Results obtained show an improvement in the number of clock cycles required when implementing on hardware/software co-design over a pure software implementation. However, using a pure hardware implementation results in a much higher performance with somewhat lower flexibility.

关键词： Adaptive filters Filtering algorithms Hardware Field programmable gate arrays Iterative algorithms Statistics Cyclones Application software Least squares approximation Software algorithms

来源：评论

学校读者我要写书评

暂无评论

FPGA-driven pseudorandom number generators aimed at accelerating Monte Carlo methods

FPGA-driven pseudorandom number generators aimed at accelera...

引用

ACS/IEEE International conference on Computer Systems and applications

作者： Tarek Ould Bachir Jean-Jules Brault Department of Electrical Engineering École Polytechnique de Montréal Montreal QUE Canada

Hardware acceleration in high performance computing (HPC) context is of growing interest, particularly in the field of Monte Carlo methods where the resort to field programmable gate array (FPGA) technology has been proven as an effective media, capable of enhancing by several orders the speed execution of stochastic processes. The spread-use of reconfigurable hardware for stochastic simulation gathered a significant effort towards effective implementations of hardware pseudorandom numbers generators (PRNGs) - these generators needed to exhibit a statistically proven random behaviour and to be characterized by a very long period. In this paper we present the state of the art of hardware pseudorandom number generation in the context of Monte Carlo acceleration. We highlight the emerging trends over the most recent publications and suggest some insights on the forthcoming works. Furthermore, we provide a complete hardware description of a new Gaussian variate generator (GVG) and an exponential variate generator (EVG) based on a decision-tree technique of ours, herein presented as well. The prototypes implemented on a Xilinx Virtex ii Pro XC2VP100 FPGA occupy from 150 to 417 slices and reach 280 MHz, while exhibiting good statistical behaviours with high p-values on the x 2 test and offering a unitary Knuth ratio.

关键词： Acceleration Hardware Field programmable gate arrays Stochastic processes Character generation Random number generation High performance computing Monte Carlo methods Prototypes Testing

来源：评论

学校读者我要写书评

暂无评论

Hardware/software co-design of an ATCA-based computation platform for data acquisition and triggering

Hardware/software co-design of an ATCA-based computation pla...

引用

IEEE NPSS conference on Real Time

作者： Qiang Wang Axel Jantsch Dapeng Jin Andreas Kopp Wolfgang Kuehn Johannes Lang Soeren Lange Lu Li Ming Liu Zhen'an Liu Zhonghai Lu David Muenchow Johannes Roskoss Hao Xu Experimental Physics Center Institute of High Energy Physics Beijing China II. Physikalisches Institut Justus-Liebig-Universitaet Giessen Germany Dept. of Electronics Royal Institute of Technology Sweden

An ATCA-based computation platform for data acquisition and trigger (TDAQ) applications has been developed for multiple future projects such as PANDA, HADES, and BESiiI. Each Compute Node (CN) appears as one of the fourteen Field Replaceable Units (FRU) in an ATCA shelf, which in total features a high performance of 1890 Gbps inter-FPGA onboard channels, 1456 Gbps inter-board backplane connections, 728 Gbps full-duplex optical links, 70 Gbps Ethernet, 140 GBytes DDR2 SDRAM, and all computing resources of 70 Xilinx Virtex-4 FX60 fpgas. Corresponding to the system architecture, a hardware/software co-design approach is proposed to ease and accelerate the development for different experiments. In the uniform system design, application-specific computation is to be implemented as customized hardware co-processors, while the embedded PowerPC processor takes charge of flexible slow controls and transmission protocol processing.

关键词： Hardware Data acquisition High performance computing Optical computing Application software Backplanes Optical fiber communication Ethernet networks SDRAM Field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共42页 << < 19 20 21 22 23 24 25 26 27 28 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：