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High-performance designs for linear algebra operations on reconfigurable hardware

IEEE TRANSACTIONS ON COMPUTERS 2008年第8期57卷 1057-1071页

作者： Zhuo, Ling Prasanna, Viktor K. Univ So Calif Ming Hsieh Dept Elect Engn Los Angeles CA 90089 USA

Numerical linear algebra operations are key primitives in scientific computing. Performance optimizations of such operations have been extensively investigated. With the rapid advances in technology, hardware acceleration of linear algebra applications using field-programmable gate arrays (fpgas) has become feasible. In this paper, we propose FPGA-based designs for several basic linear algebra operations, including dot product, matrix-vector multiplication, matrix multiplication, and matrix factorization. By identifying the parameters for each operation, we analyze the trade-offs and propose a high-performance design. In the implementations of the designs, the values of the parameters are determined according to the hardware constraints, such as the available chip area, the size of available memory, the memory bandwidth, and the number of I/O pins. The proposed designs are implemented on Xilinx Virtex-ii Pro fpgas. Experimental results show that our designs scale with the available hardware resources. Also, the performance of our designs compares favorably with that of general-purpose processor-based designs. We also show that, with faster floating-point units and larger devices, the performance of our designs increases accordingly.

关键词： reconfigurable hardware computations on matrices parallel algorithms

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Sequence alignment with traceback on reconfigurable hardware

Sequence alignment with traceback on reconfigurable hardware

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2008 International conference on reconfigurable computing and fpgas, ReConFig 2008

作者： Lloyd, Scott Snell, Quinn O. Brigham Young University Dept. of Computer Science Provo UT 84602 United States

ISBN: (纸本)9780769534749

Biological sequence alignment is an essential tool used in molecular biology and biomedical applications. The growing volume of genetic data and the complexity of sequence alignment present a challenge in obtaining alignment results in a timely manner. Known methods to accelerate alignment on reconfigurable hardware only address sequence comparison, limit the sequence length, or exhibit memory and I/O bottlenecks. A space-efficient, global sequence alignment algorithm and architecture is presented that accelerates the forward scan and traceback in hardware without memory and I/O limitations. With 256 processing elements in FPGA technology, a performance gain over 300 times that of a desktop computer is demonstrated on sequence lengths of 16000. For greater performance, the architecture is scalable to more processing elements. © 2008 IEEE.

关键词： reconfigurable hardware

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VLSI Implementation of a Cryptography-Oriented reconfigurable Array

VLSI Implementation of a Cryptography-Oriented Reconfigurabl...

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11th Euromicro conference on Digital System Design

作者： Miller, Scott Chu, Ambrose Sima, Mihai McGuire, Michael Univ Victoria Dept Elect & Comp Engn Victoria BC V8W 3P6 Canada

ISBN: (纸本)9780769532776

The long-word and very long-word addition required in cryptography applications generally requires custom hardware support provided by ASICs or application-specific instructions in ASIPs. As an altemative to these expensive solutions, fpgas have been used. To reduce the overhead of commercial fpgas in implementing cryptography, CryptoRA, a cryptographically-oriented reconfigurable array, has recently been proposed. This paper presents a circuit-level implementation of the CryptoRA array which provides the following results: (i) a speed-up of 1.15 x to 2.1 x from the LUT output to a fast-addition carry path, (ii) a speed-up greater than 1.2 x for long-word addition and subtraction, and (iii) these results come at a cost of only an additional 2.5% of a computing tile's silicon area.

关键词： Cryptography

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Universal Wavelet kernel implementation using reconfigurable hardware

Universal Wavelet kernel implementation using reconfigurable...

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2008 International conference on reconfigurable computing and fpgas, ReConFig 2008

作者： Desmouliers, Christophe Oruklu, Erdal Saniie, Jafar Department of Electrical and Computer Engineering Illinois Institute of Technology Chicago IL 60616 United States

ISBN: (纸本)9780769534749

Designing a universal embedded hardware architecture for Discrete Wavelet Transform (DWT) is a challenging problem due to the diversity among wavelet kernel filters. In this work, we present three different hardware architectures for implementing multiple wavelet kernels. The first scheme utilizes fixed, parallel hardware for all the required wavelet kernels whereas the second scheme employs a processing element (PE) based datapath that can be configured for multiple wavelet filters during run-time. The third scheme makes use of partial runtime configuration of FPGA units for dynamically programming any desired wavelet filter. We present FPGA synthesis results for simultaneous implementation of six different wavelets for the proposed methods. Performance analysis and comparison of area, timing and power results are presented for the Virtex-ii Pro FPGA implementation. © 2008 IEEE.

关键词： reconfigurable hardware

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A hardware task-graph scheduler for reconfigurable multi-tasking systems

A hardware task-graph scheduler for reconfigurable multi-tas...

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2008 International conference on reconfigurable computing and fpgas, ReConFig 2008

作者： Clemente, Juan Antonio González, Carlos Resano, Javier Mozos, Daniel Computer Architecture Department Universidad Complutense Madrid Spain

ISBN: (纸本)9780769534749

reconfigurable hardware can be used to build a multi-tasking system where tasks are assigned to HW resources at run-time according to the requirements of the running applications. These tasks are frequently represented as direct acyclic graphs and their execution is typically controlled by an embedded processor that schedules the graph execution. In order to improve the efficiency of the system, the scheduler can apply prefetch and reuse techniques that can greatly reduce the reconfiguration latencies. For a processor all these computations represent a heavy computational load that can significantly reduce the system performance. To overcome this problem we have implemented a HW scheduler using reconfigurable resources. In addition we have implemented both prefetch and replacement techniques that obtain as good results as previous complex SW approaches, while demanding just a few clock cycles to carry out the computations. We consider that the HW cost of the system (in our experiments 3% of a Virtex-ii PRO xc2vp30 FPGA) is affordable taking into account the great efficiency of the techniques applied to hide the reconfiguration latency and the negligible run-time penalty introduced by the scheduler computations. © 2008 IEEE.

关键词： Multitasking

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Leveraging firmware in multichip systems to maximize FPGA resources: An application of self-partial reconfiguration

Leveraging firmware in multichip systems to maximize FPGA re...

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2008 International conference on reconfigurable computing and fpgas, ReConFig 2008

作者： Galindo, Juan Peskin, Eric Larson, Brad Roylance, Gene Rochester Institute of Technology 79 Lomb Memorial Drive Rochester NY 14623 United States Hewlett-Packard 11311 Chinden Boulevard Boise ID 83714 United States

ISBN: (纸本)9780769534749

A number of SRAM-based field programmable gate arrays (fpgas) allow for partial reconfiguration (PR). Partial reconfiguration can be used to maximize the resource utilization in these fpgas. Current methodologies use both external and self partial reconfiguration for this purpose. On mature multichip (MC) systems that have not made use of the PR features of their SRAM-based FPGA(s), however, these methodologies would require changes in the existing FPGA configuration protocol and/or associated hardware outside the array. This paper presents a novel methodology that makes PR features available to these systems for the purpose of maximizing their FPGA resources without the modifications required by the current methodologies. The proposed methodology reuses an existing data interface to send the PR data to the array and directs this data to the FPGA's internal configuration port. A prototype of this methodology is demonstrated on a commercial color space conversion (CSC) engine design using two Xilinx Virtex-ii Pro fpgas. © 2008 IEEE.

关键词： Firmware

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Disparity map hardware accelerator

Disparity map hardware accelerator

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2008 International conference on reconfigurable computing and fpgas, ReConFig 2008

作者： Calderón, Humberto Ortiz, Jesús Fontaine, Jean-Guy IIT - Italian Institute of Technology TERA - TEle Robotics and Applications Dept. Via Morego 30 16163 Genoa Italy

ISBN: (纸本)9780769534749

Hardwired acceleration units capable of exploiting the parallelism of images rely on highly customized memory organizations. In this paper we analyze a widely used depth-discontinuity-algorithm applied in stereo vision systems. The main processing kernels are decomposed, and a hardwired acceleration unit is proposed for speeding up the computation. The hardware accelerator includes multiple arithmetic comparison and absolute difference units, as well as a customized memory organization. The proposed micro-organization was instantiated using a XA3S500E Spartan 3E FPGA device. The obtained results show that by implementing this new hardwired algorithm a processing acceleration of 268 times is achieved for the targeted kernel, while the solution uses 30 % of the chosen FPGA device. The baseline comparison was the pure software execution over a Microblaze soft core processor based on the same FPGA technology. © 2008 IEEE.

关键词： Acceleration

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Analysis and enhancement of random number generator in FPGA based on oscillator rings

Analysis and enhancement of random number generator in FPGA ...

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2008 International conference on reconfigurable computing and fpgas, ReConFig 2008

作者： Wold, Knut Tan, Chik How NISlab Department of Computer Science and Media Technology Gjøvik University College Norway

ISBN: (纸本)9780769534749

A true random number generator (TRNG) is an important component in cryptographic systems. Designing a fast and secure TRNG in an FPGA is a challenging task. In this paper we analyze the TRNG designed by Sunar et al. [12] based on XOR of the outputs of many oscillator rings. We propose an enhanced TRNG that does not require post-processing to pass statistical tests and with better randomness characteristics on the output. We have shown by experiment that the frequencies of the equal length oscillator rings in the TRNG are not identical but different due to the placement of the inverters in the FPGA. We have implemented our proposed TRNG in an Altera Cyclone ii FPGA. Our implementation has passed the NIST and DIEHARD statistical tests with a throughput of 100Mbps and with a usage of less than 100 logic elements in the FPGA. © 2008 IEEE.

关键词： Field programmable gate arrays (FPGA)

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reconfigurable Instruction Set Processor Design Using Software Based Configuration

Reconfigurable Instruction Set Processor Design Using Softwa...

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International conference on Advanced Computer Theory and Engineering (ICACTE 2008)

作者： Iqbal, M. Aqeel Awan, Uzma Saeed Faculty of Engineering and Information Technology Foundation University Institute of Engineering and Management Sciences

ISBN: (纸本)9780769534893

Due to the potential enhancements in the execution of software based applications shown by reconfigurable Instruction Set Processors (RISPs), reconfigurable computing has become a subject of great deal of research in the field of computer sciences. Its key feature is the ability to perform the computations in hardware to increase, the performance on one hand while retaining much of the flexibility of the software on the other hand The VLSI development is continuously improving and new ways must be obtained to become able to fully take the advantages of the emerging technology. reconfigurable hardware might be the next step which will give computer performance a big leap forward. The idea is to use the now a day's high performance FPGA technology to adapt the hardware to the problem. This research paper presents an alternative design of a RISP which supports multiple threads running concurrently, all with instant hardware support. Core of Xilinx fpgas like Virtex series has been used to adapt the possibilities of loading partial hardware configurations while retaining the execution of the remaining active parts of the application.

关键词： Fine-grain Coarse-grain Configurations FPGA RFUs RISP Multi-port Configuration Memory

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Synthesis of Application Accelerators on Runtime reconfigurable Hardware

Synthesis of Application Accelerators on Runtime Reconfigura...

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19th IEEE International conference on Application-Specific Systems, Architectures and Processors

作者： Alle, Mythri Varadarajan, Keshavan Reddy, Ramesh Joseph, Nimmy Fell, Alexander Rao, Adarsha Nandy, S. K. Narayan, Ranjani Indian Inst Sci SERC CAD Lab Bangalore 560012 Karnataka India Morphing Machines Bangalore Karnataka India

ISBN: (纸本)9781424418978

Application accelerators are predominantly ASICs. The cost of ASIC solutions are order of magnitudes higher than programmable processing cores. Despite this, ASIC solutions are preferred when both high performance and low power is the target. ASICs offer no flexibility in terms of it being able to cater to application derivatives, unless this has been provisioned for at the time of design. In this paper we define the architecture of Runtime reconfigurable Hardware (RRH) as the platform for application acceleration. The proposed RRH is a homogeneous fabric comprising computing, storage and communicating resources. We also propose a synthesis methodology to realize application written a high level language (HLL) on the RRH. applications described in HLL is compiled into application substructures. For each application substructure a set of Compute Elements interconnected in a manner that closely matches the communication pattern within it, is allocated CEs in such a configuration is called a hardware affine. Hardware Affines are carved out on the RRH at runtime. These hardware affines are defined at compile time, and are provisioned at runtime on the fabric. By virtue of the fact that these hardware affines are NOT instruction set processor cores or Logic Elements as in fpgas, we bear the performance and power advantage of an ASIC, and the hardware reconfigurability/programmability of that of an FPGA/Instruction Set Processor.

关键词： reconfigurable hardware

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