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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

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reconfigurable Cell Architecture for Systolic and Pipelined computing Datapaths

Reconfigurable Cell Architecture for Systolic and Pipelined ...

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： Abdulrahman Hanoun Friedrich Mayer-Lindenberg Bassel Soudan Institute of Computer Technology Hamburg University of Technology Hamburg Germany Electrical and Computer Engineering University of Sharjah Sharjah UAE

This paper introduces a reconfigurable computing cell architecture for pipelined and systolic datapaths in the mixed grained reconfigurable coprocessor array system (MiGCop). The cell is efficiently capable of building scalable parallel-parallel, serial-parallel, and serial-serial signed multipliers. Several cells can be combined to form a reconfigurable coprocessor that is tightly coupled with clusters of specially-designed lightweight RISC processors. In this paper, we present two different cell structures and compare their implementations using the 0.13 mum standard cell CMOS technology from Faraday reg and select the design with the most efficient area-delay product for the emerging MiGCop system. We will show that the cells are capable of computation frequencies higher than 250 MHz at a reasonable power consumption.

关键词： Computer architecture Hardware Coprocessors Energy consumption Fabrics Control systems Costs CMOS technology Parallel processing Computer applications

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Forward-Secure Content Distribution to reconfigurable Hardware

Forward-Secure Content Distribution to Reconfigurable Hardwa...

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： David Champagne Reouven Elbaz Catherine Gebotys Lionel Torres Ruby B. Lee Princeton University USA University of Waterloo Canada LIRMM CNRS-University of Montpellier II France

Confidentiality and integrity of bitstreams and authenticated update of FPGA configurations are fundamental to trusted computing on reconfigurable technology. In this paper, we propose to provide these security services for digital content broadcast to FPGA-based devices. To that end, we introduce a new property we call forward security, which ensures that broadcast content can only be accessed by FPGA chips configured with the latest bitstream version. We describe the hardware architecture and communication protocols supporting this security property, and we evaluate the associated cost.

关键词： Hardware Field programmable gate arrays Broadcasting Security Cryptography Costs Distributed computing Communication channels Streaming media DVD

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Sequence Alignment with Traceback on reconfigurable Hardware

Sequence Alignment with Traceback on Reconfigurable Hardware

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： Scott Lloyd Quinn O. Snell Department of Computer Science Brigham Young University Provo UT USA

Biological sequence alignment is an essential tool used in molecular biology and biomedical applications. The growing volume of genetic data and the complexity of sequence alignment present a challenge in obtaining alignment results in a timely manner. Known methods to accelerate alignment on reconfigurable hardware only address sequence comparison, limit the sequence length, or exhibit memory and I/O bottlenecks. A space-efficient, global sequence alignment algorithm and architecture is presented that accelerates the forward scan and traceback in hardware without memory and I/O limitations. With 256 processing elements in FPGA technology, a performance gain over 300 times that of a desktop computer is demonstrated on sequence lengths of 16000. For greater performance, the architecture is scalable to more processing elements.

关键词： Hardware Sequences Acceleration Field programmable gate arrays Genetics Databases Biology computing Systolic arrays DNA Computer architecture

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Leveraging Firmware in Multichip Systems to Maximize FPGA Resources: An Application of Self-Partial Reconfiguration

Leveraging Firmware in Multichip Systems to Maximize FPGA Re...

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： Juan Galindo Eric Peskin Brad Larson Gene Roylance Rochester Institute of Technology Rochester NY USA Hewlett Packard Company Boise ID USA

A number of SRAM-based field programmable gate arrays (fpgas) allow for partial reconfiguration (PR). Partial reconfiguration can be used to maximize the resource utilization in these fpgas. Current methodologies use both external and self partial reconfiguration for this purpose. On mature multichip (MC) systems that have not made use of the PR features of their SRAM-based FPGA(s), however, these methodologies would require changes in the existing FPGA configuration protocol and/or associated hardware outside the array. This paper presents a novel methodology that makes PR features available to these systems for the purpose of maximizing their FPGA resources without the modifications required by the current methodologies. The proposed methodology reuses an existing data interface to send the PR data to the array and directs this data to the FPGApsilas internal configuration port. A prototype of this methodology is demonstrated on a commercial color space conversion (CSC) engine design using two Xilinx Virtex-ii Pro fpgas.

关键词： Microprogramming Field programmable gate arrays reconfigurable logic Bills of materials Prototypes Hardware Resource management Flash memory Ethernet networks Logic arrays

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Disparity Map Hardware Accelerator

Disparity Map Hardware Accelerator

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Humberto Calderón Jesús Ortiz Jean-Guy Fontaine TERA-TEle Robotics and Applications Department IIT-Italian Institute of Technology Genoa Italy

Hardwired acceleration units capable of exploiting the parallelism of images rely on highly customized memory organizations. In this paper we analyze a widely used depth-discontinuity-algorithm applied in stereo vision systems. The main processing kernels are decomposed, and a hardwired acceleration unit is proposed for speeding up the computation. The hardware accelerator includes multiple arithmetic comparison and absolute difference units, as well as a customized memory organization. The proposed micro-organization was instantiated using a XA3S500E Spartan 3E FPGA device. The obtained results show that by implementing this new hardwired algorithm a processing acceleration of 268 times is achieved for the targeted kernel, while the solution uses 30 % of the chosen FPGA device. The baseline comparison was the pure software execution over a Microblaze soft core processor based on the same FPGA technology.

关键词： Hardware Acceleration Field programmable gate arrays Concurrent computing Kernel Bandwidth Pixel Parallel processing Arithmetic Delay

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Universal Wavelet Kernel Implementation Using reconfigurable Hardware

Universal Wavelet Kernel Implementation Using Reconfigurable...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Christophe Desmouliers Erdal Oruklu Jafar Saniie Department of Electrical and Computer Engineering Illinois Institute of Technology Chicago IL USA

Designing a universal embedded hardware architecture for discrete wavelet transform (DWT) is a challenging problem due to the diversity among wavelet kernel filters. In this work, we present three different hardware architectures for implementing multiple wavelet kernels. The first scheme utilizes fixed, parallel hardware for all the required wavelet kernels whereas the second scheme employs a processing element (PE) based datapath that can be configured for multiple wavelet filters during run-time. The third scheme makes use of partial runtime configuration of FPGA units for dynamically programming any desired wavelet filter. We present FPGA synthesis results for simultaneous implementation of six different wavelets for the proposed methods. Performance analysis and comparison of area, timing and power results are presented for the Virtex-ii Pro FPGA implementation.

关键词： Kernel Hardware Discrete wavelet transforms Filters Field programmable gate arrays Matrix converters Matrix decomposition Computer architecture Runtime Wavelet transforms

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The hardware application platform of the hartes project

The hardware application platform of the hartes project

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International conference on Field Programmable Logic and applications

作者： Immacolata Colacicco Giacomo Marchiori Raffaele Tripiccione Dipartimento di Fisica Università degli Studi di Ferrara Ferrara Italy

We describe the hardware platform that will be used to run several demonstrator applications within the EU-funded hArtes project. hArtes' main goal is to support, with appropriate tools, the development of complex applications on heterogeneous and reconfigurable systems. Our platform provides a number of heterogeneous computing sub-systems, such as DSPs, general-purpose CPUs and configurable elements (in the shape of fpgas). The envisaged applications are mainly in the audio realm, so support for high-quality audio I/O is also present. fpgas play a dual role: i) they support I/O functions for audio streaming, moving audio signals from/to main memory with full hardware support; ii) tightly coupled to traditional processors, they make up the reconfigurable processing core within the system. This paper describes the architecture and the first implementation of the platform.

关键词： Field programmable gate arrays Program processors Digital signal processing Hardware Computer architecture Reduced instruction set computing Ethernet networks

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Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings

Analysis and Enhancement of Random Number Generator in FPGA ...

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： Knut Wold Chik How Tan NISlab Department of Computer Science and Media Technology GjE28885vik University College Norway

A true random number generator (TRNG) is an important component in cryptographic systems. Designing a fast and secure TRNG in an FPGA is a challenging task. In this paper we analyze the TRNG designed by Sunar et al. based on XOR of the outputs of many oscillator rings. We propose an enhanced TRNG that does not require post-processing to pass statistical tests and with better randomness characteristics on the output. We have shown by experiment that the frequencies of the equal length oscillator rings in the TRNG are not identical but different due to the placement of the inverters in the FPGA. We have implemented our proposed TRNG in an Altera Cyclone ii FPGA. Our implementation has passed the NIST and DIEHARD statistical tests with a throughput of 100 Mbps and with a usage of less than 100 logic elements in the FPGA.

关键词： Random number generation Field programmable gate arrays Ring oscillators Logic testing Cryptography Frequency Inverters Cyclones NIST Throughput

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A Hardware Task-Graph Scheduler for reconfigurable Multi-tasking Systems

A Hardware Task-Graph Scheduler for Reconfigurable Multi-tas...

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： Juan Antonio Clemente Carlos González Javier Resano Daniel Mozos Computer Architecture Department Universidad Complutense de Madrid Madrid Spain

reconfigurable hardware can be used to build a multi-tasking system where tasks are assigned to HW resources at run-time according to the requirements of the running applications. These tasks are frequently represented as direct acyclic graphs and their execution is typically controlled by an embedded processor that schedules the graph execution. In order to improve the efficiency of the system, the scheduler can apply prefetch and reuse techniques that can greatly reduce the reconfiguration latencies. For a processor all these computations represent a heavy computational load that can significantly reduce the system performance. To overcome this problem we have implemented a HW scheduler using reconfigurablere sources. In addition we have implemented both prefetch and replacement techniques that obtain as good results as previous complex SW approaches, while demanding just a few clock cycles to carry out the computations. We consider that the HW cost of the system (in our experiments 3% of a Virtex-ii PRO xc2vp30 FPGA) is affordable taking into account the great efficiency of the techniques applied to hide there configuration latency and the negligible run-time penalty introduced by the scheduler computations.

关键词： Hardware Processor scheduling Runtime Delay Prefetching Field programmable gate arrays Personal communication networks Computer architecture Application software System performance

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Dynamic Critical-Path Based on Fit Degree Scheduling for reconfigurable Multi-fpgas

Dynamic Critical-Path Based on Fit Degree Scheduling for Rec...

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International conference on Application of Concurrency to System Design

作者： Yan Xiao Zhenhua Duan Institute of computing theory and technology Xidian University Xidian China

ISBN: (纸本)9781424418381

reconfigurable computing is becoming increasingly attractive for many applications. In this paper, an efficient algorithm named dynamic critical-path based on fit degree (DCPFD) is formalized and used to schedule related hardware tasks in terms of task graphs for reconfigurable fpgas with respect to the constraints: precedence, deadline and resource. The dynamic critical-path (DCP) dynamically evaluates critical-paths of a task graph and determines the most critical task in order to shorten the schedule length. The fit degree (FD) is calculated for the scheduled task w.r.t each FPGA, and used to check which FPGA has enough space and where in it, to place the task. The Pre-fetching technique is also employed to reduce the FPGA configuration overhead.

关键词： Dynamic scheduling Processor scheduling Field programmable gate arrays Computer architecture Signal processing algorithms Hardware Digital signal processing Fabrics Switches Data flow computing

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