检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

408 篇 会议
9 篇 期刊文献
1 篇 学位论文

馆藏范围

418 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

221 篇 工学
- 210 篇 计算机科学与技术...
- 100 篇 软件工程
- 49 篇 电气工程
- 49 篇 电子科学与技术（可...
- 22 篇 控制科学与工程
- 17 篇 信息与通信工程
- 12 篇 动力工程及工程热...
- 7 篇 土木工程
- 5 篇 光学工程
- 5 篇 建筑学
- 5 篇 航空宇航科学与技...
- 5 篇 生物工程
- 4 篇 机械工程
- 4 篇 环境科学与工程（可...
- 3 篇 仪器科学与技术
- 2 篇 生物医学工程（可授...
66 篇 理学
- 39 篇 数学
- 17 篇 物理学
- 6 篇 生物学
- 6 篇 系统科学
- 4 篇 统计学（可授理学、...
- 2 篇 化学
- 1 篇 地球物理学
- 1 篇 地质学
13 篇 管理学
- 13 篇 管理科学与工程(可...
- 9 篇 工商管理
3 篇 经济学
- 3 篇 应用经济学
3 篇 医学
- 3 篇 临床医学
2 篇 教育学
- 2 篇 教育学
1 篇 法学
- 1 篇 社会学

主题

149 篇 field programmab...
96 篇 hardware
69 篇 computer archite...
35 篇 field programmab...
32 篇 application soft...
32 篇 fpga
24 篇 reconfigurable a...
20 篇 runtime
20 篇 acceleration
19 篇 parallel process...
19 篇 reconfigurable c...
16 篇 routing
16 篇 digital signal p...
15 篇 high performance...
14 篇 concurrent compu...
14 篇 reconfigurable l...
14 篇 random access me...
14 篇 clocks
12 篇 bandwidth
12 篇 microprocessors

机构

7 篇 department of co...
5 篇 george washingto...
4 篇 institute for re...
3 篇 rochester instit...
3 篇 george mason uni...
3 篇 karlsruhe instit...
3 篇 xilinx inc san j...
2 篇 heinz nixdorf in...
2 篇 chengdu universi...
2 篇 northeastern uni...
2 篇 brocade communic...
2 篇 department of el...
2 篇 institute of com...
2 篇 embedded softwar...
2 篇 department of el...
2 篇 variel microelec...
2 篇 institut für tec...
2 篇 institute for se...
2 篇 faculty of elect...
2 篇 department of el...

作者

9 篇 luk wayne
6 篇 wayne luk
4 篇 cheung peter y. ...
4 篇 axel jantsch
4 篇 zhonghai lu
4 篇 t. el-ghazawi
4 篇 ming liu
4 篇 peter y. k. cheu...
4 篇 wolfgang kuehn
3 篇 s.j. visser
3 篇 david kearney
3 篇 sonia lopez
3 篇 a.s. dawood
3 篇 j.a. williams
3 篇 john wawrzynek
3 篇 e. el-araby
3 篇 sven-ole voigt
3 篇 shaoyi cheng
3 篇 w. luk
3 篇 prasanna viktor ...

语言

411 篇 英文
7 篇 其他

检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

共 418 条记录，以下是251-260 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks

Reconfigurable platforms and the challenges for large-scale ...

引用

International conference on Field Programmable Logic and applications

作者： Jim Harkin Fearghal Morgan Steve Hall Piotr Dudek Thomas Dowrick Liam McDaid Bio-Inspired Electronics Reconfigurable Computing Group NUI Galway Ireland Intelligent Systems Research Centre University of Ulster UK Institute for Nanoscale Science Engineering & Technology University of Liverpool UK School of Electrical and Electronic Engineering University of Manchester Institute of Science and Technology UK

FPGA devices have witnessed popularity in their use for the rapid prototyping of biological Spiking Neural Network (SNNs) applications, as they offer the key requirement of reconfigurability. However, fpgas do not efficiently realise the biological neuron/synaptic models. Also their routing structures cannot accommodate the high levels of neuron inter-connectivity inherent in complex SNNs. This paper highlights and discusses the current challenges of implementing large scale SNNs on reconfigurable fpgas. The paper presents a novel Field Programmable Neural Network (FPNN) architecture incorporating low power analogue synapse and a network on chip architecture for SNN routing and configuration. Initial results are presented.

关键词： Neurons Tiles Computer architecture Field programmable gate arrays Biology Hardware Integrated circuit interconnections

来源：评论

学校读者我要写书评

暂无评论

SPP1148 booth: Coarse-grained reconfiguration

SPP1148 booth: Coarse-grained reconfiguration

引用

International conference on Field Programmable Logic and applications

作者： Sven Eisenhardt Thomas Schweizer Julio A. de Oliveira Filho Tobias Oppold Wolfgang Rosenstiel Alexander Thomas Jurgen Becker Frank Hannig Dmitrij Kissler Hritam Dutta Jurgen Teich Heiko Hinkelmann Peter Zipf Manfred Glesner Department of Computer Engineering University of Tuebingen Germany ITIV Department of EE & IT University of Karlsruhe Germany Hardware/Software Co design Department of Computer science University of Erlangen-Nuremberg Germany MES Department of EE & IT Darmstadt University of Technology Germany

ISBN: (纸本)9781424419606

In the last years, aside from fine-grained reconfigurable architectures such as fpgas, coarse-grained reconfigurable architectures (CGRAs), which typically have building blocks of a fixed bit-width (8 bit, 16 bit, etc.), have gained in importance in academia as well as in industry. CGRAs are usually used for domain-specific computations and have advantages over traditional fpgas in terms of area and power cost, performance, and reconfiguration time. Thus, architectures with coarse-grained reconfiguration features have also been studied in projects (Sec. 1, 2, 4) within the priority program reconfigurable computing Systems and the project CoMap (Sec. 3), which are all sponsored by the German science foundation.

关键词： Computer architecture Hardware Energy efficiency Runtime Field programmable gate arrays Microprocessors conferences

来源：评论

学校读者我要写书评

暂无评论

Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip

Metawire: Using FPGA configuration circuitry to emulate a Ne...

引用

International conference on Field Programmable Logic and applications

作者： M. Shelburne C. Patterson P. Athanas M. Jones B. Martin R. Fong Bradley Department of Electrical & Computer Engineering Configurable Computing Laboratory Virginia Technology Blacksburg VA USA

ISBN: (纸本)9781424419606

While there have been many reported implementations of networks-on-chip (NoCs) on fpgas, they have not seen the same acceptance as NoCs on ASICs. One reason is that communication on an FPGA is already costly due to the die resources and time delays inherent in the reconfigurable structure. Layering another general-purpose network on top of the reconfigurable network simply incurs too many performance penalties. There is, however, already a largely unused, global network available in fpgas. As a proof-of-concept, we demonstrate that the Xilinx FPGA configuration circuitry, which is normally idle during system operation, can function as a relatively high-performance NoC. MetaWire performs transfers through an overclocked Virtex-4 internal configuration access port (ICAP) and is shown to provide a bandwidth exceeding 200 MBytes/sec.

关键词： Field programmable gate arrays Magnetic cores Throughput Bandwidth Random access memory Routing Wires

来源：评论

学校读者我要写书评

暂无评论

VLSI Implementation of a Cryptography-Oriented reconfigurable Array

VLSI Implementation of a Cryptography-Oriented Reconfigurabl...

引用

Euromicro Symposium on Digital System Design

作者： Scott Miller Ambrose Chu Mihai Sima Michael McGuire Department of Electrical and Computer Engineering University of Victoria Victoria Canada

The long-word and very long-word addition required in cryptography applications generally requires custom hardware support provided by ASICs or application-specific instructions in ASIPs. As an alternative to these expensive solutions, fpgas have been used. To reduce the overhead of commercial fpgas in implementing cryptography, CryptoRA, a cryptographically-oriented reconfigurable array, has recently been proposed. This paper presents a circuit level implementation of the CryptoRA array which provides the following results: (i) a speed-up of 1.15times to 2.1times from the LUT output to a fast-addition carry path, (ii) a speed-up greater than 1.2times for long-word addition and subtraction, and (iii) these results come at a cost of only an additional 2.5% of a computing tile's silicon area.

关键词： Very large scale integration Elliptic curve cryptography Tiles Field programmable gate arrays Table lookup Computer architecture Costs Silicon Logic Personal digital assistants

来源：评论

学校读者我要写书评

暂无评论

Optimizing residue arithmetic on fpgas

Optimizing residue arithmetic on FPGAs

引用

IEEE International conference on Field-Programmable technology (FPT)

作者： Haohuan Fu Oskar Mencer Wayne Luk Department of Computing Imperial College London London UK

Residue number system (RNS), which originates from the Chinese remainder theorem, is regarded as a promising number representation in the domain of digital signal processing (DSP). This paper describes our work on optimizing residue arithmetic units on the platform of reconfigurable devices, such as fpgas. First, we provide improved designs for residue arithmetic units. For reverse converters from RNS to binary numbers, we propose a novel design that uses only n-bit additions. Compared to previous work, the design consumes up to 14.3% less area and provides lower latency. Second, we develop a reconfigurable RNS arithmetic library generator for the moduli set {2 n -1, 2 n , 2 n +1}. The generator supports a wide range of RNS numbers, and enables us to perform an extensive comparison between RNS and other number representations at both the arithmetic unit level and the application level. The comparison shows that, for applications involving a large number of multiplications, the RNS designs can reduce up to 1/2 DSP48s for large bit-width settings.

关键词： Arithmetic Field programmable gate arrays Libraries Digital signal processing Signal processing algorithms Delay Cathode ray tubes Design optimization Sun Equations

来源：评论

学校读者我要写书评

暂无评论

Classification of Application Development for FPGA-Based Systems

Classification of Application Development for FPGA-Based Sys...

引用

IEEE National conference on Aerospace and Electronics (NAECON)

作者： Ivan Gonzalez Esam El-Araby Proshanta Saha Tarek El-Ghazawi Harald Simmler Saumil G. Merchant Brian M. Holland Casey Reardon Alan D. George Herman Lam Greg Stitt Nahid Alam Melissa C. Smith NSF Center for High-Performance Reconfigurable Computing (CHREC) The George Washington University USA NSF Center for High-Performance Reconfigurable Computing (CHREC) The George Washington University NSF Center for High-Performance Reconfigurable Computing (CHREC) University of Florida Clemson University

Field-programmable gate arrays (fpgas) have been used to accelerate DoD-related applications with promising performance. However, current development tools require significant hardware knowledge and are not amenable to the increasing complexity of FPGA-based systems. The application requirements are expected to change dramatically for future use cases, and require a well defined development methodology. This paper presents the results obtained after conducting an extensive survey and study about current FPGA tools. A classification for DoD use cases and FPGA tools is provided. This classification provides the current status of the available tools and identifies current tool limitations for DoD use cases.

关键词： Field programmable gate arrays High performance computing Hardware Space technology Algorithm design and analysis Costs Government Acceleration Computer aided software engineering Mission critical systems

来源：评论

学校读者我要写书评

暂无评论

Exploiting the SoC capability of high performance fpgas - a video case study

Exploiting the SoC capability of high performance FPGAs - a ...

引用

2008 IET and Electronics Weekly conference on Programmable Hardware Systems

作者： Peter Brookes Altera European Technology Centre Multimedia System Solution Group

As high performance applications become increasingly complex, reconfigurable computing must evolve to address the industry's shifting needs. Multi-layered FPGA SoC platforms can enable rapid system development and provide the designer with control over their own differentiating IP. This presentation will describe the key challenges faced by today's video system designers and how FPGA technologies can deliver both fast time to market and high performance processing. Specifically, a video framework is described targeting representative multi-stream video processing applications.

关键词： video equipment computer software Software design Designers jigs(templates) HIGH-PERFORMANCE presentation Videotapes Frameworks debugger design tools Field programmable gate arrays system level

来源：评论

学校读者我要写书评

暂无评论

Leakage power estimation and minimization in configurable logic block of FPGA

Leakage power estimation and minimization in configurable lo...

引用

International conference on Computer and Communication Engineering, ICCCE

作者： A. K. Kureshi Mohd. Hasan Department of Electronics Engineering Aligarh Muslim University Aligarh India

reconfigurable architectures are well suited for wireless application since they provide high performance computation together with the capability to adapt to changing communication protocols. Moving to deep sub-micron technology and below, FPGA could suffer from leakage energy consumption. This paper estimates the extensive transistor level leakage power of Virtex-ii fpgas Configurable Logic Block (CLB) at 65 nm technology and, also explore different techniques to minimize leakage power. HSPICE simulations based on BPTM (Berkeley Predictive technology Model) at 25degC and 85degC shows that, for worst-case data, techniques such as high threshold voltage (HV T ), high gate-oxide (HT ox ) and Gate biasing (NVGS) improve the leakage power saving by up to 65.70%, 70.53% and 31.85% with average delay penalty of 15.40%, 26.24% and 0% respectively.

关键词： Minimization Field programmable gate arrays Predictive models reconfigurable logic reconfigurable architectures High performance computing Wireless application protocol Energy consumption Threshold voltage Delay

来源：评论

学校读者我要写书评

暂无评论

reconfigurable Instruction Set Processor Design Using Software Based Configuration

Reconfigurable Instruction Set Processor Design Using Softwa...

引用

International conference on Advanced Computer Theory and Engineering, ICACTE

作者： M. Aqeel Iqbal Uzma Saeed Awan Institute of Engineering and Management Sciences Faculty of Engineering and Information Technology Foundation University Netherlands

Due to the potential enhancements in the execution of software based applications shown by reconfigurable Instruction Set Processors (RISPs), reconfigurable computing has become a subject of great deal of research in the field of computer sciences. Its key feature is the ability to perform the computations in hardware to increase the performance on one hand while retaining much of the flexibility of the software on the other hand. The VLSI development is continuously improving and new ways must be obtained to become able to fully take the advantages of the emerging technology. reconfigurable hardware might be the next step which will give computer performance a big leap forward. The idea is to use the now a daypsilas high performance FPGA technology to adapt the hardware to the problem. This research paper presents an alternative design of a RISP which supports multiple threads running concurrently, all with instant hardware support. Core of Xilinx fpgas like Virtex series has been used to adapt the possibilities of loading partial hardware configurations while retaining the execution of the remaining active parts of the application.

关键词： Software design Process design Hardware Computer aided instruction Field programmable gate arrays Application software Software performance Very large scale integration Computer performance Yarn

来源：评论

学校读者我要写书评

暂无评论

Exploring New Architectures in Accelerating CFD for Air Force applications

Exploring New Architectures in Accelerating CFD for Air Forc...

引用

DoD High Performance computing Modernization Program Users Group

作者： Jack Dongarra Gregory Peterson Stanimir Tomov Jeff Allred Vincent Natoli David Richie University of Tennessee Knoxville TN USA Bel Air Stone Ridge Technology MD USA

Computational fluid dynamics (CFD) is an active field of research where the development of faster and more accurate methods is linked to the continuous demand for ever higher computational power. And indeed, for at least two decades, HPC programmers have taken for granted that each successive generation of microprocessors would, either immediately or after minor adjustments, make their software run substantially faster. But recent microprocessor design trends including the introduction of multi/many-core designs and the increasingly popular use in HPC of accelerators such as general purpose graphics processing units (GPGPU) and field programmable gate arrays (fpgas), present an unprecedented challenge, namely how to update and enhance the existing large CFD software infrastructure to efficiently use these new architectures. In this paper we address some main issues in this transition and present ideas on using the new architectures to accelerate CFD applications that are of interest to the air force. We consider not only multi/many-core but also special purpose (e.g., GPUs) and reconfigurable computing (e.g., fpgas) architectures.

关键词： Acceleration Computational fluid dynamics Field programmable gate arrays Computer architecture Microprocessors Parallel processing Hardware Concurrent computing Military computing Graphics

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共42页 << < 22 23 24 25 26 27 28 29 30 31 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：