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IEEE International conference on Parallel and Distributed computing, applications and Technologies (PDCAT)

作者： Maxim Leonov Vyacheslav V. Kitaev Engineering Research Institute Auckland University of Technology Auckland New Zealand

The paper provides an insight to implementation framework and a test-bed of multi-channel correlation on high-performance CPU+FPGA hybrid platform. Solution based on commodity PC, PCIe Altera Stratix ii GX board, and ... 详细信息

关键词： Digital signal processing Field programmable gate arrays Hardware Computer architecture Correlators Digital signal processing chips Wideband Paper technology Signal processing Energy management

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An efficient run-time router for connecting modules in fpgas

An efficient run-time router for connecting modules in FPGAS

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International conference on Field Programmable Logic and applications

作者： Jorge Suris Cameron Patterson Peter Athanas Bradley Department of Electrical and Computer Engineering Configurable Computing Laboratory Virginia Technology Blacksburg VA USA

ISBN: (纸本)9781424419606

It is often desirable to change the logic and/or the connections within an FPGA design on-the-fly without the benefit of a workstation or vendor CAD software. This paper presents a dynamic router for Xilinx fpgas, designed to run on stand-alone embedded systems. With information obtained from Xilinxpsilas XDL tool, a compact routing database for the Virtex-ii/iiP/4 devices is built which only requires 96 KB of storage. A channel routing algorithm is used because of its deterministic execution time and because all routing resources in the channel are available. Sample channels are routed with the router and compared with the Xilinx PAR tool. Improvements in both execution time and in memory usage of several orders of magnitude are observed.

关键词： Routing Databases Switches Field programmable gate arrays Wire Delay Propagation delay

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ATCA-based computation platform for data acquisition and triggering in particle physics experiments

ATCA-based computation platform for data acquisition and tri...

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International conference on Field Programmable Logic and applications

作者： Ming Liu Johannes Lang Shuo Yang Tiago Perez Wolfgang Kuehn Hao Xu Dapeng Jin Qiang Wang Lu Li Zhen'An Liu Zhonghai Lu Axel Jantsch II. Physics Institute Justus-Liebig-University Giessen Germany Dept. of Electronic Computer and Software Systems Royal Institute of Technology Sweden Experimental Physics Center Institute of High Energy Physics in Beijing Beijing China Experimental Physics Center Institute of High Energy Physics in Beijing China

ISBN: (纸本)9781424419606

An ATCA-based computation platform for data acquisition and trigger applications in nuclear and particle physics experiments has been developed. Each compute node (CN) which appears as a field replaceable unit (FRU) in an ATCA shelf, features 5 Xilinx Virtex-4 FX60 fpgas and up to 10 GBytes DDR2 memory. Connectivity is provided with 8 optical links and 5 Gigabit Ethernet ports, which are mounted on each board to receive data from detectors and forward results to outer shelves or PC farms with attached mass storage. Fast point-to-point on-board interconnections between fpgas as well as the full-mesh shelf backplane provide flexibility and high bandwidth to partition algorithms and correlate results among them. The system represents a highly reconfigurable and scalable solution for multiple applications.

关键词： Field programmable gate arrays Physics Program processors Feature extraction Ethernet networks Algorithm design and analysis Linux

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Adaptivity and reliability in future chips. Multi-core and reconfigurable architectures in the Nano Era

Adaptivity and reliability in future chips. Multi-core and r...

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IET Irish Signals and Systems conference (ISSC 2008)

作者： Jurgen Becker Karlsruhe Institute of Technology Germany

Summary form only given. The field of embedded electronic systems is still emerging. Multipurpose adaptivity and reliability features are playing more and more of a central role, especially while scaling silicon technologies down according to Moore's benchmarks. Leading processor and mainframe companies are gaining more awareness of reconfigurable computing technologies due to increasing energy and cost constraints. The author's view is of an "all-win-symbiosis" of future silicon- based processor technologies and reconfigurable circuits/architectures. Dynamic and partial reconfiguration has progressed from academic labs to industry research and development groups, providing high adaptivity for a range of applications and situations. Reliability, failure-redundancy and run-time adaptivity using real-time hardware reconfiguration are important aspects for current and future systems. Thus, scalability, as we have experienced for the last 35 years is at its end as we enter the so-called Nano Era. Beyond the capabilities of traditional reconfigurable fabrics (like fpgas), nano circuits/architectures allow for micro-mechanical switches that enable new memory and reconfiguration technologies with the advantage of online chip adaptivity and non-volatility. The deployment of new 3-D nano structures and materials promises higher integration densities and is considered advantageous for signal delays. Yield is significantly lower, and could, as we define it in the classical sense, eventually be nil! Transient faults may lead to unreliable information processing as information in nano-sized devices is much less. Power consumption and related problems present a challenge where information is processed within a smaller area/volume budget. Thus, novel design methodologies, novel adaptive mechanisms which solve operation-time shortcomings, and novel computing paradigms are necessary. Fault tolerance/correction in all its facets is key and should be considered an inherent technique i

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Dynamic partial FPGA reconfiguration in a prototype microprocessor system

Dynamic partial FPGA reconfiguration in a prototype micropro...

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17th International conference on Field Programmable Logic and applications

作者： Schleupen, Kai Lekuch, Scott Mannion, Ryan Guo, Zhi Najjar, Walid Vahid, Frank IBM System and Technology Group Department of Computer Science and Engineering University of California Riverside United States Brocade Communications System

ISBN: (纸本)9781424410590

Modem fpgas' parallel computing capability and their ability to be reconfigured make them an ideal platform to build accelerators for supercomputing systems. As a multicore processor, the recently announced Cell Broadband EngineTM1 offers tremendous computing power. In this paper, we introduce a prototype system that combines these two types of computing devices together in a reconfigurable blade and we describe its architecture, memory system and abundant interfaces. On the reconfigurable blade it is desirable that the FPGA devices can be partially reconfigured at run-time. This paper presents the dynamic partial reconfiguration (DPR) technique and its design flow for the reconfigurable blade. We report our experimental results of the blade doing partial reconfiguration. DPR allows the reconfigurable blade to be a powerful, run-time changeable computing engine. A sample application is presented that was both simulated for the Cell processor and dynamically loaded to run on the FPGA.

关键词： Field programmable gate arrays (FPGA)

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An overview of a compiler for mapping software binaries to hardware

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2007年第11期15卷 1177-1190页

作者： Mittal, Gaurav Zaretsky, David Tang, Xiaoyong Banerjee, Prith Univ Illinois Dept Elect & Comp Engn Chicago IL 60607 USA Binachip Inc Kyoto 60601 Japan Magma Design Automat San Jose CA 95110 USA Univ Illinois Coll Engn Chicago IL 60607 USA

As new applications in embedded communications and control systems push the computational limits of digital signal processing (DSP) functions, there will be an increasing need for software applications to be migrated to hardware in the form of a hardware-software codesign system. In many cases, access to the high-level source code may not be available. It is thus desirable to have a technology to translate the software binaries intended for processors to hardware implementations. This paper provides details on the retargetable FREEDOM compiler. The compiler automatically translates DSP software binaries to register-transfer level (RTL) VHDL and Verilog for implementation on field-programmable gate arrays (fpgas) as standalone or system-on-chip implementations. We describe the underlying optimizations and some novel algorithms for alias analysis, data dependency analysis, memory optimizations, procedure call recovery, and back-end code scheduling. Experimental results on resource usage and performance are shown for several program binaries intended for the Texas Instruments C6211 DSP (VLIW) and the ARM 922T reduced instruction set computer (RISC) processors. Implementation results for four kernels from the Simulink demo library and others from commonly used DSP applications, such as MPEG-4, Viterbi, and JPEG are also discussed. The compiler generated RTL code is mapped to Xilinx Virtex ii and Altera Stratix fpgas. We record overall performance gains of 1.5-26.9 x for the hardware implementations of the kernels. Comparisons with the power aware compiler techniques (PACT) high-level synthesis compiler are used to show that software binaries can be used as intermediate representations from any high-level language and generate efficient hardware implementations.

关键词： binary translation compiler decompilation hardware-software codesign high-level synthesis reconfigurable computing

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Circuit switched run-time adaptive network-on-chip for image processing applications

Circuit switched run-time adaptive network-on-chip for image...

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17th International conference on Field Programmable Logic and applications

作者： Braun, Lars Huebner, Michael Becker, Juergen Perschke, Thomas Schatz, Volker Bach, Stefan Univ Karlsruhe ITIV Engesserstr 5 D-76131 Karlsruhe Germany Forschungs Inst Optron & Mustererkennung D-76275 Ettlingen Germany

ISBN: (纸本)9781424410590

Since the 1990s reusable functional blocks, well known as IP-Cores, have been integrated on one silicon die. These Systems-on-Chip (SoC) used a bus-based system for inter-module communication. technology, performance and flexibility issues require the introduction of a novel communication system called Network-on-Chip (NoC). A-round 1999 this method was introduced and since then has been investigated by several research groups with the aim to connect different EP-Cores through an effective, flexible and scalable communication network. Exploiting the flexibility of fpgas, the run-time adaptivity through run-time reconfiguration, opens a new area of research by considering dynamic and partial reconfiguration. Since software parts of an electronic system can also be included into reconfigurable hardware by integration of IP-based microcontrollers, the reconfigurable architecture provides a flexible, multi-adaptive heterogeneous platform for HW / SW Co-designs. This paper presents an approach for exploiting dynamic and partial reconfiguration with Xilinx Virtex-ii fpgas for an adaptive circuit switched Network-on-Chip and the related techniques for adapting the system during run-time to the requirements of the presented image processing application.

关键词： Network-on-chip

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reconfigurable Trusted computing in Hardware

Reconfigurable Trusted Computing in Hardware

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ACM Workshop on Scalable Trusted computing

作者： Eisenbarth, Thomas Gueneysu, Tim Paar, Christof Sadeghi, Ahmad-Reza Schellekens, Dries Wolf, Marko Ruhr Univ Bochum Horst Gortz Inst IT Secur Bochum Germany

ISBN: (纸本)9781595938886

Trusted computing (TC) is an emerging technology towards building trustworthy computing platforms. The Trusted computing Group (TCG) has proposed several specifications to implement TC functionalities by extensions to common computing platforms, particularly the underlying hardware with a Trusted Platform Module (TPM). However, actual TPMs are mostly available for workstations and servers nowadays and rather for specific domain applications and not primarily for embedded systems. Further, the TPM specifications are becoming monolithic and more complex while the applications demand a scalable and flexible usage of TPM functionalities. In this paper we propose a reconfigurable (hardware) architecture with TC functionalities where we focus on TPMs as proposed by the TCG specifically designed for embedded platforms. Our approach allows for (i) an efficient and scalable design and update of TPM functionalities, in particular for hardware-based crypto engines and accelerators, (ii) establishing a minimal trusted computing base in hardware, (iii) including the TPM as well as its functionalities into the chain of trust that enables to bind sensitive data to the underlying reconfigurable hardware, and (iv) designing a manufacturer independent TPM. We discuss possible implementation based on current FPCAs and point out the associated challenges, in particular with respect to protection of the internal TPM state since it must not be subject to manipulation, replay, and cloning.

关键词： Field Programmable Gate Array (FPGA) Trusted computing Trusted Platform Module (TPM)

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An efficient placement algorithm for run-time reconfigurable embedded system

An efficient placement algorithm for run-time reconfigurable...

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19th IASTED International conference on Parallel and Distributed computing and Systems

作者： Guha, Radha Bagherzadeh, Nader Chou, Pai EECS Dept. University of California Irvine CA 92697 United States

ISBN: (纸本)9780889867048

In the era of application convergence, the small handheld battery-powered portable devices are required to multiplex their limited hardware resources between many complex applications. Our first contribution in this paper is a modular and block based configuration architecture for modern fpgas like Xilinx's Virtex-4 and Virtex-5 devices, to increase multi-tasking capabilities, power savings and performance improvement of applications for mobile handsets. Our second contribution is an on-line placement algorithm based on bin packing, called Hierarchical Best Fit Ascending (HBFA) algorithm, which is more efficient than Best Fit (BF) algorithm for mapping a dynamic task list onto the FPGA. The overall time complexity of the proposed on-line placement algorithm, HBFA, is reduced to O(n) in comparison to the complexity of BF algorithm which is O(n2). The placement solution provided by HBFA algorithm is also better than that of BF algorithm.

关键词： Field programmable gate arrays (FPGA)

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Supporting fault-tolerant on-board evolution in aerospace reconfigurable platform

Supporting fault-tolerant on-board evolution in aerospace re...

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IET conference on Wireless, Mobile and Sensor Networks 2007, CCWMSN'07

作者： Peng, Liu Guojun, Dai Tingting, Fu Xiang, Zhang Institute of Computer Application Technology Hangzhou Dianzi University Hangzhou 310018 China Institute of Graphics and Image Hangzhou Dianzi University Hangzhou 310018 China

ISBN: (纸本)9780863418365

Due to long distance and terrible environment, it is difficult to maintain spacecrafts once they were launched. Traditional On-board Software Maintenance (OBSM) often fails because of broken communication and unexpected situation. This has generated a pressing need for self-adaptive, self-repairing and self-upgrading capabilities in On-Board Maintenance (OBM) applications. In this paper, we propose a fault-tolerant on-board evolutionary platform which implements relocation of hardware and software tasks in spaceborne computing systems. Tasks can either run in software space or be put into hardware task slots according to energy-efficient or real-time requirements. The allocation of hardware and software tasks will evolve in terms of current condition to meet real-time, energy-efficient or environment requirements. Sleeping tasks, redundant fpgas and version switching control are combined together to achieve fault-tolerance in the on-board evolutionary platform. The design theories and strategies of proposed prototype are described in detail. Simulation and experiment results are discussed as well.

关键词： Fault tolerance

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