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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

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Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan iiI fpgas

Implementation of a Virtual Internal Configuration Access Po...

引用

International conference on Field Programmable Logic and applications

作者： K. Paulsson M. Hubner G. Auer M. Dreschmann L. Chen J. Becker Institute for Information Processing Technology Universität Karlsruhe Germany

The exploitation of dynamic and partial hardware reconfiguration on fpgas is currently being investigated in various research projects, dealing with systems for space applications to automotive and masurement applications. Despite challenges such as a complicated design flow, dynamic reconfigurable systems offer advantages in terms of flexibility and performance. Unfortunately only few kinds of commercial architectures support dynamic and partial reconfiuration, which has lead to Virtex ii / IV being main target architectures for this kind of systems. Additionally, the Xilinx Spartan iiI architecture is dynamically and partially reconfigurable with some limitations, one of them being the lack of an internal configuration port. The Virtex ii / IV and V architectures all include the ICAP port, which allows a system to reconfigure itself during run-time without additional external components. Until now, this was not possible on the Spartan iiI architecture. This paper presents the implementation of a virtual internal configuration port for the Spartan iiI family of fpgas. The configuration port was implemented for a hardware reconfigurable measurement system, which is implemented on a Spartan iiI FPGA due to its cost-and power optimized characteristics.

关键词： Field programmable gate arrays Hardware Vehicle dynamics reconfigurable architectures Space technology Energy consumption Computer architecture Cost function Information processing Automotive engineering

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Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System

Dynamic Partial FPGA Reconfiguration in a Prototype Micropro...

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International conference on Field Programmable Logic and applications

作者： Kai Schleupen Scott Lekuch Ryan Mannion Zhi Guo Walid Najjar Frank Vahid IBM System & Technology Group USA University of California Riverside USA Brocade Communications System USA

Modern fpgas' parallel computing capability and their ability to be reconfigured make them an ideal platform to build accelerators for supercomputing systems. As a multi-core processor, the recently announced Cell Broadband EngineTMl offers tremendous computing power. In this paper, we introduce a prototype system that combines these two types of computing devices together in a reconfigurable blade and we describe its architecture, memory system and abundant interfaces. On the reconfigurable blade it is desirable that the FPGA devices can be partially reconfigured at run-time. This paper presents the dynamic partial reconfiguration (DPR) technique and its design flow for the reconfigurable blade. We report our experimental results of the blade doing partial reconfiguration. DPR allows the reconfigurable blade to be a powerful, run-time changeable computing engine. A sample application is presented that was both simulated for the Cell processor and dynamically loaded to run on the FPGA.

关键词： Field programmable gate arrays Prototypes Microprocessors Blades Runtime Parallel processing Multicore processing Computer interfaces Computer architecture Memory architecture

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Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing applications

Circuit Switched Run-Time Adaptive Network-on-Chip for Image...

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International conference on Field Programmable Logic and applications

作者： Lars Braun Michael Hubner Jurgen Becker Thomas Perschke Volker Schatz Stefan Bach ITIV Universitaet Karlsruhe Karlsruhe Germany Forschungsinstitut für Optronik und Mustererkennung Ettlingen Germany

Since the 1990s reusable functional blocks, well known as IP-Cores, have been integrated on one silicon die. These systems-on-chip (SoC) used a bus-based system for intermodule communication. technology, performance and flexibility issues require the introduction of a novel communication system called network-on-chip (NoC). Around 1999 this method was introduced and since then has been investigated by several research groups with the aim to connect different IP-Cores through an effective, flexible and scalable communication network. Exploiting the flexibility of fpgas, the run-time adaptivity through run-time reconfiguration, opens a new area of research by considering dynamic and partial reconfiguration. Since software parts of an electronic system can also be included into reconfigurable hardware by integration of IP-based microcontrollers, the reconfigurable architecture provides a flexible, multi-adaptive heterogeneous platform for HW / SW Co-designs. This paper presents an approach for exploiting dynamic and partial reconfiguration with Xilinx Virtex-ii fpgas for an adaptive circuit switched network-on-chip and the related techniques for adapting the system during run-time to the requirements of the presented image processing application.

关键词： Switching circuits Runtime Adaptive systems Network-on-a-chip Image processing Field programmable gate arrays Communication switching Silicon Communications technology Integrated circuit technology

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Accelerating tool path computing in CAD/CAM: A FPGA architecture for turning lathe machining

Accelerating tool path computing in CAD/CAM: A FPGA architec...

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International conference on Field Programmable Logic and applications

作者： Antonio Jimeno-Morenilla Antonio Martinez Sergio Cuenca Jose Luis Sanchez-Romero Computer Science Technology and Computation Department University of Alicante Alicante Spain

Tool path generation is one of the most complex problems in computer aided manufacturing. The algorithm called virtual digitizing avoids this problem by its own definition but its computing cost is high. Presented in the paper there is a virtual digitizing hardware/software architecture that takes advantage of field programmable gate arrays (fpgas) to improve the algorithm efficiency and to meet the current restrictions of the traditional no standard machines. In order to evaluate the architecture, a prototype was implemented using a commercial reconfigurable platform integrated within a numerically controlled lathe for shoe last machining. The performance of the system for tool path generation was measured for different trajectories and surface precisions using a database of real shoe models. The experiments show a significant speedup, keeping the computing error below the system tolerance.

关键词： Acceleration Computer aided manufacturing CADCAM Field programmable gate arrays Turning Machining Footwear Costs Hardware Software architecture

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Dynamically reconfigurable Dataflow Architecture for High-Performance Digital Signal Processing on Multi-FPGA Platforms

Dynamically Reconfigurable Dataflow Architecture for High-Pe...

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International conference on Field Programmable Logic and applications

作者： Sven-Ole Voigt Thomas Teufel Institute for Reliable Computing Hamburg University of Technology Hamburg Germany

In this paper we present an FPGA-based dataflow architecture that both efficiently computes parallel algorithms using dedicated FPGA resources and scales well to multi-FPGA chip designs while the overall communication bandwidth increases. The basic idea is based on reconfiguration. In contrast to the concept of partially reconfiguring fpgas, our approach is to connect computational units via a dynamically variable topology. The latter consists of dedicated switches which are individually controlled by simple shift registers. Hence, the computational result is a function of the currently configured interconnection pattern that can be updated within one single clock cycle. The scalability of this architecture is shown on a high-performance parallel FFT.

关键词： Digital signal processing Computer architecture Field programmable gate arrays Digital signal processing chips Concurrent computing Parallel algorithms Chip scale packaging Bandwidth Topology Switches

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A Framework for the Design of Distributed reconfigurable Embedded Systems

A Framework for the Design of Distributed Reconfigurable Emb...

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20th International conference on Architecture of computing Systems 2007

作者： Alessandro Cilardo Luigi Coppolino Nicola Mazzocca University of Naples Federico II Italy

Recent trends in embedded systems architectures are increasingly based on FPGA technologies extending traditional ASIC cores and providing reconfigurable hardware support for performance demanding applications such as multimedia and network or security processing. In this paper, we propose a new framework for the design and management of hardware reconfigurability in distributed embedded environments. The essential aim of the framework is to abstract away the details of the underlying FPGA technology and expose a register transfer level view of the hardwareüaccelerated blocks, allowing the software layer to extract, manipulate, and even export the hardware/software execution state at runütime. The paper also presents some caseüstudy scenarios emphasizing the benefits enabled by the proposed framework for the design of distributed embedded systems.

关键词： Hardware Field programmable gate arrays Java Mobile communication Computer architecture Embedded systems

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A Case for Soft Vector Processors in fpgas

A Case for Soft Vector Processors in FPGAs

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IEEE International conference on Field-Programmable technology (FPT)

作者： Jason Yu Guy Lemieux Department of Electrical and Computer Engineering University of British Columbia Vancouver Canada

Embedded applications today require high computational power that is not met by current FPGA-based soft processors. Although performance of data-parallel applications can be addressed by custom-designed hardware accelerators, such an approach is difficult for embedded software developers with little hardware design experience. Instead, vector processing can be used to speed up these same data-parallel applications. The vector programming model is easy to understand by software developers, making it easier for them to extract the parallelism without any hardware design knowledge. This paper proposes a soft vector processor for the Stratix iiI FPGA that can be scaled to different levels of performance and resource utilization. It has several configurable features that can be included or excluded to optimize the soft processor for a given application. Performance estimates of the soft vector processor using three embedded benchmark kernels show speedup of up to 16.6 x over an idealized Nios ii processor while using 10.9 x the area.

关键词： Vector processors Field programmable gate arrays Application software Hardware Embedded computing Embedded software Parallel programming Parallel processing Resource management Kernel

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A Hardware-based Architecture to Support Flexible Real-Time Parallel Intrusion Detection

A Hardware-based Architecture to Support Flexible Real-Time ...

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2007 IEEE International conference on System of Systems Engineering (SOSE 2007), vol.2

作者： Stephen Mott Samuel Hart David Montminy Paul Williams Rusty Baldwin Air Force Institute of Technology OH USA

Providing security in today's complex computing systems is a daunting task As systems (of systems) grow both increasingly pervasive and complex, defending them from attack or mischance at the systems of systems level becomes ever more challenging. We propose moving some security monitoring tasks from software to hardware which will allow real time detection of intrusions and errors. Our flexible architecture uses reconfigurable logic (such as field programmable gate arrays (fpgas)) and operates in parallel with a general purpose computing environment. To that end, new hardware primitives are proposed that allow for gathering and monitoring the state of the main processor transparently (that is, the main processor is unaware of the monitoring) in real time. The result is a decrease in workload for the main processor while enhancing security. The monitoring primitives are tightly coupled with the monitored software, and can readily and automatically respond to changes in system characteristics such as new software applications or devices. By focusing on specific system components, including their interface with other system components, we believe we can enhance system of system security in ways not readily achievable using conventional, system-wide monitoring techniques.

关键词： Intrusion detection Security Hardware Computerized monitoring Operating systems Computer architecture Real time systems Concurrent computing Field programmable gate arrays Programmable logic arrays

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Hardware/Software Co-design of a General-Purpose Computation Platform in Particle Physics

Hardware/Software Co-design of a General-Purpose Computation...

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IEEE International conference on Field-Programmable technology (FPT)

作者： Ming Liu Wolfgang Kuehn Zhonghai Lu Axel Jantsch Shuo Yang Tiago Perez Zhenan Liu II. Physics Institute Justus Liebig University Giessen Germany Department of Electronic Computer and Software Systems Royal Institute of Technology Sweden Experimental Physics Center Institute for High Energy Physics China

In this paper we present a hardware/software co-design based computation platform for online data processing in particle physics experiments. Our goal is to ease and accelerate the development and make it universal and scalable for multiple applications, on the premise of guaranteeing high communicating and processing capabilities. The entire computation network consists of quite a few interconnected compute nodes, each of which has multiple fpgas to implement specific algorithms for data processing. High-speed communication features including RocketIO multi-gigabit transceiver and Gigabit Ethernet are supported by fpgas to construct internal and external connections. An embedded Linux operating system is fitted on the PowerPC CPU core inside the Xilinx Virtex-4 FX FPGA. Thus programmers can access hardware resources via device drivers and write application programs to manage the system from the high level. Furthermore measurements have been executed using the development board to investigate both communicating and processing performances of the system. Results show that the computation platform is able to communicate at a UDP/IP data rate of around 400 Mbps per Ethernet link, and the event selection engine could process an event stream of 148.1 MBytes/s at an interesting event rate of 25%.

关键词： Hardware Physics computing Field programmable gate arrays Data processing Computer networks Ethernet networks Acceleration Application software Power system interconnection Transceivers

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Dynamic Reconfiguration in Sensor Networks with Regenerative Energy Sources

Dynamic Reconfiguration in Sensor Networks with Regenerative...

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Design, Automation and Test in Europe conference and Exhibition

作者： Ani Nahapetian Paolo Lombardo Andrea Acquaviva Luca Benini Majid Sarrafzadeh Computer Science Department University of California Los Angeles Los Angeles CA USA Dipartimento di Elettronica Informatica e Sistemistica (DEIS) Universitá Bologna Bologna Italy Information Science and Technology Institute (ISTI) Universitá di Urbino Urbino Italy

ISBN: (纸本)9783981080124

In highly power constrained sensor networks, harvesting energy from the environment makes prolonged or even perpetual execution feasible. In such energy harvesting systems, energy sources are characterized as being regenerative. Regenerative energy sources fundamentally change the problem of power scheduling for embedded devices. Instead of the problem being one of maximizing the lifetime of the system given a total amount of energy, as in traditional battery powered devices, the problem becomes one of preventing energy depletion at any given time. Coupling relatively computationally intensive applications, such as video processing applications, with the constrained fpgas that are feasible on power constrained embedded systems, makes dynamic reconfiguration essential. It provides the speed comparable to a hardware implementation, but it also allows the dynamic reconfiguration to meet the multiple application needs of the system. Different applications can be loaded on the FPGA, as the system's needs change over time. The problem becomes how to schedule the dynamic reconfiguration to appropriately make use of the regenerative energy source, to ensure the proper availability of energy for the system over time. This paper presents a methodology for carrying out dynamic reconfiguration for regenerative energy sources, based on statistical analysis of tasks and supply energy. The approach is evaluated through extensive simulations. Additionally, the implementation has been evaluated on regenerative energy, dynamically reconfigurable prototype, known as the MicrelEye. The approach is shown to miss 57.7% less deadlines on average than the current approach for reconfiguration with regenerative energy sources

关键词： Sensor phenomena and characterization Field programmable gate arrays Processor scheduling Batteries Computer applications Embedded computing Embedded system Hardware Dynamic scheduling Statistical analysis

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