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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

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Parallel Implementation of 2D-DWT by Purging Read after Write Dependency for High Speed applications

Parallel Implementation of 2D-DWT by Purging Read after Writ...

引用

International conference on Emerging Technologies, ICET

作者： M. Ashraf M. Shamim Baig Liaqat Ali Khan Ali Hassan Center for Cyber Technology and Spectrum Management National University of Science and Technology Islamabad Pakistan Center for Cyber Technology and Spectrum Management National University of Science and Technology Islamabad

ISBN: (纸本)1424414935

This paper proposes an efficient implementation of multistage, multiple-level DSP algorithms suitable for parallel and distributed processing. To describe our method we selected Mallat's algorithm for two dimensional wavelet transforms (2D-DWT) coefficient computation which has multistage and multilevel processing requirements. We have selected field programmable gate arrays (FPGA) as a processing unit because of its inherited parallel processing capabilities but our method is not limited to fpgas only. Our method directly computes 2D-DWT coefficients without computing and storing intermediate results; which makes it faster; resource saving and removes read after Write (RAW) dependencies. We discuss multistage and single level implementation but ideally it can be extended to n-level implementation. We also proposed method for generation of "mutually scaled filter coefficients (MSFC)" and computation of maximum number of parallel processors for optimized performance in this particular case. Both lookup tables (LUTs) and multipliers along with addition/subtraction architecture can be used. However, LUTs have advantage of high processing speed. Two computational stages are combined into a single stage to remove read after write (RAW) dependency. Our implementation takes N 2 /4+L 2 /4-2 time units to compute 2D- DWT of N x N input data, with filter length of L without intermediate storage. This method can be used for other multistage, multilevel DSP problems. Quartusreg ii IDE and Altera Stratix device is used for implementation.

关键词： Field programmable gate arrays Table lookup Digital signal processing Filters Distributed processing Wavelet transforms Parallel processing Concurrent computing Optimization methods Computer architecture

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The reconfigurable computing applied to the learning in the computer engineering program

The Reconfigurable Computing applied to the learning in the ...

引用

7th International conference on Information technology Based Higher Education and Training

作者： Pilla, Valfredo, Jr. Ferlin, Edson P. UnicenP Ctr Univ Posit Dept Comp Engn Rua Prof Pedro Viriato Parigot de Souza 5300 BR-81280330 Curitiba Parana Brazil

ISBN: (纸本)9781424404056

The reconfigurable computing has an increasing importance in the computational solutions because of its two mains characteristics: performance and flexibility. This became possible with the technological advance of the Programmable Logic Devices (PLDs) and the Field Programmable Gate Array (fpgas), which makes possible an increasing level of system integration (hardware and software). This integration can allow the construction of a complex system in a single device, the System on Chip (SoC) technology. This is a multidisciplinary area, because it involves digital systems projects (some time analog systems also), firmware and operational systems development, beyond the specific knowledge of the areas of the systems applications. For this reasons the reconfigurable computation became part of the computer engineer formation. It is imperative that the new professionals have complete domain of this technology to be able to integrate it in the new computational systems. These computational systems reach a wide range of applications, from high performance computing to embedded systems, personal and mobile computation, to entertainment and mobile communication. In this direction, we present the evolution that happened in the Computer Engineering Program at UnicenP from the adoption of the technology of PLDs and fpgas in several courses, and the inclusion of a specific course of reconfigurable computing.

关键词： embedded systems learning in engineering programmable logic reconfigurable computing

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Hardware join Java: A unified Hardware/Software language for dynamic partial runtime reconfigurable computing applications

Hardware join Java: A unified Hardware/Software language for...

引用

5th IEEE International conference on Field Programmable technology

作者： Kearney, David Hopf, John Univ South Australia Adv Comp Res Ctr Mawson Lakes SA Australia

ISBN: (纸本)9780780397286

reconfigurable computing is maturing rapidly as fpgas combining hard core processors and high density logic block arrays become widely available at low cost Application developers have been developing algorithms that cross the hardware software divide for some years but will in addition want to express the dynamic reconfiguration of fpgas made available via an operating system for reconfigurable computing. Whilst there are many behavioural languages available or expressing reconfigurable computing applications very few of them are comprehensive enough to address simultaneously these two requirements. In this paper we present an experimental language based on Java which aims to achieve the twin goals of a transparent hardware software interface and an integrated expression of dynamic reconfiguration. Hardware Join Java (HJJ) uses a common threading abstraction and synchronization based on the Join calculus to unify the semantics and interface between hardware and software. The language extends the dynamic class instantiation mechanism of Java (supported by the services of an operating system for reconfigurable computing) to express user initiated dynamic reconfiguration of the FPGA. In this paper we present basic syntax and semantics of HJJ and give our initial experience with the prototype compiler.

关键词： Java programming language

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On reconfigurable architectures for efficient matrix inversion

On reconfigurable architectures for efficient matrix inversi...

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16th International conference on Field Programmable Logic and applications

作者： de Matos, Goncalo M. Neto, Horacio C. Univ Tecn Lisboa INESC ID IST P-1100 Lisbon Portugal

ISBN: (纸本)9781424403127

This paper presents an analysis of the performance of the Gauss-Jordan matrix inversion algorithm on reconfigurable hardware platforms. ne results show that currently available reconfigurable computing technology can already achieve significantly higher floating-point performance than CPUs for large matrices operations. For common reconfigurable systems, where the fpgas are directly coupled to the on-board memory, the achievable performance scales directly with the number of realizable simultaneous memory accesses. A dedicated reconfigware architecture has been implemented and tested on a standard commercial reconfigurable platform. Even though the platform used had limited data bandwidth between the FPGA and the on-board memory, speed improvements of more than 3x have been observed, in comparison with software solutions running in high-end CPUs, for the inversion of matrices of orders up to 1700.

关键词： reconfigurable architectures

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Virtex iiFPGA bitstream manipulation: Application to reconfiguration control systems

Virtex IIFPGA bitstream manipulation: Application to reconfi...

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16th International conference on Field Programmable Logic and applications

作者： Krasteva, Y. E. de la Torre, E. Riesgo, T. Joly, Didier Univ Politecn Madrid Grp Elect Ind Madrid Spain Memondo Graph Inc Madrid Spain

ISBN: (纸本)9781424403127

This paper presents a tool for Virtex ii (Pro) FPGA partial bitstream manipulation suited for reconfigurable control systems with limited computing resources. The basics for partial bitstream manipulation in Virtex H (Pro) fpgas are shown, including bit allocation equations that could be used to create such tools. After that, a tool for partial bitstream manipulation, called pBITPOS, and a use case in a reconfigurable control system are described. Differently from other non Virtex 11 (Pro) solutions, this tool can be integrated in a reconfiguration control system, running on an embedded device, and it can handle BRAM/MULs related data.

关键词： Field programmable gate arrays (FPGA)

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The learning of reconfigurable computing in the computer engineering program

The learning of reconfigurable computing in the computer eng...

引用

36th ASEE/IEEE Frontiers in Education conference, FIE

作者： Ferlin, Edson Pedro Pilla Jr., Valfredo Computer Engineering Department Centro Universitário Positivo - UnicenP Rua Prof. Pedro Viriato Parigot de Souza 5300 Curitiba PR 81280-330 Brazil

ISBN: (纸本)1424402565

The reconfigurable computing has an increasing importance in the computational solutions because of its two main characteristics: performance and flexibility. This became possible with the technological advance of the Complex Programmable Logic Devices (CPLDs) and the Field Programmable Gate Array (fpgas), which makes possible an increasing level of system integration (hardware and software). This integration can allow the construction of a complex system in a single device, the System on Chip (SoC) technology. This is a multidisciplinary area, because it involves digital systems projects (some time analog systems also), firmware and operational systems development, beyond the specific knowledge of the areas of the systems applications. For this reasons the reconfigurable computation became part of the computer engineer formation. It is imperative that the new professionals have complete domain of this technology to be able to integrate it in the new computational systems. These computational systems reach a wide range of applications, from high performance computing to embedded systems, personal and mobile computing, to entertainment and mobile communication. In this direction, we present the evolution that happened in the Computer Engineering Program at UnicenP from the adoption of the technology of CPLDs and fpgas in several courses, and the inclusion of a specific reconfigurable computing Course. © 2006 IEEE.

关键词： Firmware

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An FPGA implementation of linear kernel support vector machines

An FPGA implementation of linear kernel support vector machi...

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3rd IEEE International conference on reconfigurable computing and fpgas

作者： Pina-Ramirez, Omar Valdes-Cristerna, Raquel Yanez-Suarez, Oscar Univ Autonoma Metropolitana Iztapalapa Neuroimaging Lab Mexico City 09370 DF Mexico

ISBN: (纸本)1424406897

This paper describes preliminary performance results of a reconfigurable hardware implementation of a support vector machine classifier aimed at brain-computer interface applications, which require real-time decision making in a portable device. The main constraint of the design was that it could perform a classification decision within the time span of an evoked potential recording epoch of 300 ms, which was readily achieved for moderate-sized support vector sets. Regardless of its fixed-point implementation, the FPGA-based model achieves equivalent classification accuracies to those of its software-based, floating-point counterparts.

关键词： reconfigurable hardware

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Robust ultra-low power subthreshold logic flip-flop design for reconfigurable architecture

Robust ultra-low power subthreshold logic flip-flop design f...

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3rd IEEE International conference on reconfigurable computing and fpgas

作者： Chavan, Ameet Dukle, Gaurav Graniello, Ben MacDonald, Eric Univ Texas El Paso TX 79968 USA Intel Corp Chandler AZ USA

ISBN: (纸本)1424406897

Low power consumption and radiation hardness are generally competing requirements for space electronics as well as many Earth-bound high reliability applications. Fault tolerance typically requires redundancy and reconfigurability to ensure correct functional operation in the presence of errors. However, this runs contrary to the requirement for reduced power consumption in many battery-powered applications. Recently, subthreshold logic has emerged as a technology that delivers the theoretical minimum energy per computation by running at ultra-low voltages. For many applications, the resulting performance degradation is tolerable due the dramatic increase in energy efficiency. Beyond the concerns with performance, an additional challenge is related to radiation hardness and noise immunity. The marriage of subthreshold logic and reconfigurahle, high-reliability electronics is inevitable, yet there has been to date no investigation of the effects of radiation on circuits that operate at such low voltages. This paper provides a comprehensive comparison of a variety of flip-flop designs at subthreshold levels.

关键词： reconfigurable architectures

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Combined integer and floating point multiplication architecture(CIFM) for fpgas and its reversible logic implementation

Combined integer and floating point multiplication architect...

引用

49th IEEE International Midwest Symposium on Circuits and Systems

作者： Thapliyal, Himanshu Arabnia, Hamid R. Vinod, A. P. IIIT Ctr VLSI Design Hyderabad Andhra Pradesh India Univ Georgia Dept Comp Sci Athens GA 30602 USA Nanyang Technol Univ Sch Comp Engn Singapore Singapore

ISBN: (纸本)9781424401727

In this paper, the authors propose the idea of a combined integer and floating point multiplier(CIFM) for fpgas. The authors propose the replacement of existing 18x18 dedicated multipliers in fpgas with dedicated 24x24 multipliers designed with small 4x4 bit multipliers. It is also proposed that for every dedicated 24x24 bit multiplier block designed with 4x4 bit multipliers, four redundant 4x4 multiplier should be provided to enforce the feature of self repairability (to recover from the faults). In the propose CIFM reconfigurability at run time is also provided resulting in low power. The major source of motivation for providing the dedicated 24x24 bit multiplier stems from the fact that single precision floating point multiplier requires 24x24 bit integer multiplier for mantissa multiplication. A reconfigurable, self-repairable 24x24 bit multiplier (implemented with 4x4 bit multiply modules) will ideally suit this purpose, making fpgas more suitable for integer as well floating point operations. A dedicated 40 bit multiplier is also proposed in this paper. Moreover, in the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. It is not possible to realize quantum computing without reversible logic. Thus, this paper also paper provides the reversible logic implementation of the proposed CIFM. The reversible CIFM designed and proposed here will form the basis of the completely reversible fpgas.

关键词： Network architecture

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Proceedings - 2006 International conference on Field Programmable Logic and applications, FPL

Proceedings - 2006 International Conference on Field Program...

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2006 International conference on Field Programmable Logic and applications, FPL

ISBN: (纸本)142440312X

The proceedings contain 168 papers. The topics discussed include: fpgas at 65nm and beyond- powerful new fpgas bring new challenges;rapid system-on-a-programmable-chip development and hardware acceleration of ANSI functions;FPGA architecture design methodology;enhanced architectures, design methodologies and CAD tools for dynamic reconfiguration on XILINK fpgas;65nm fpgas,a look under the hood: technology, features, and applications;improved interpolation and system integration for FPGA-based molecular dynamics simulations;high performance scientific computing using fpgas with IEEE floating point and logarithmic architecture for lattice QCD;placement and timing for fpgas considering variations;FPGA performance optimization via chipwise placement considering process variations;and architecture exploration and tools for pipelined coarse-grained reconfigurable arrays.

关键词： Field programmable gate arrays (FPGA)

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