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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

共 418 条记录，以下是21-30 订阅

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FPGA Architecture to Enhance Hardware Acceleration for Machine Learning applications 5

FPGA Architecture to Enhance Hardware Acceleration for Machi...

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5th International conference on computing Methodologies and Communication, ICCMC 2021

作者： Itagi, Anirudh Krishvadana, S. Bharath, K P Rajesh Kumar, M. Vellore Institute of Technology Alumni School of Electronics Engineering VelloreTN India Vellore Institute of Technology School of Electronics Engineering VelloreTN India

ISBN: (纸本)9781665403603

Many algorithms have been developed in the field of Machine learning and its sub-fields such as neural networks, Deep learning and so on, for applications such as pattern classification, image and video processing, statistical data mining and so forth. These algorithms perform such tasks with remarkable accuracy. However, when implemented in traditional processor core software, many of these algorithms get choked when the size of the network or computational demand of the algorithm scales up. fpgas and ASICs offer higher computation capability, throughput and bandwidth. Features such as massive parallel processing, high performance and reliability, are strong arguments for fpgas for Deep Neural Network applications. fpgas offer reconfigurable, flexible architectures where even the most popular GPUs fall short. This paper proposes a robust, re-configurable architecture for deploying Machine learning algorithms and presents its advantages by implementing a Neural Network in an FPGA and comparing its results with an implementation in a Raspberry Pi. © 2021 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Performance Modeling and Scalability Analysis of Stream computing in ESSPER FPGA Clusters

Performance Modeling and Scalability Analysis of Stream Comp...

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IEEE International conference on Field-Programmable technology (FPT)

作者： Ryota Miyagi Ryota Yasudo Kentaro Sano Hideki Takase The University of Tokyo Tokyo Japan Kyoto University Kyoto Japan RIKEN Kobe Japan

ESSPER is a flexible and scalable FPGA cluster system designed for reconfigurable HPC, with customizability, scalability, and interoperability with existing HPC systems. The inherent characteristics of ESSPER make it a superior alternative for achieving highly scalable computing solutions, particularly for compute-intensive applications such as numerical simulations and machine learning. However, constraints in communication bandwidth or latency can impact performance and scalability. This paper builds upon a previous performance model study to analyze performance modeling and scalability of streaming computation using a 1D ring of cascaded fpgas with high-speed, low-latency communication links in ESSPER. For evaluation and verification, we implemented a simple vector addition on ESSPER. The Result indicates that measured performance metrics closely align with predictions from the performance model. This model can also be used to estimate performance for other ESSPER applications.

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FPGA-based Accelerator for FFT-Processing in Edge computing

FPGA-based Accelerator for FFT-Processing in Edge Computing

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IEEE International Workshop on Intelligent Data Acquisition and Advanced computing Systems: technology and applications

作者： Peter Schulz Grigore Sleahtitchi HAW Hamburg Hamburg

Edge computing bridges the gap between end devices on the Internet of Things (IoT) and central, server-based IT services by accelerating tasks which otherwise could not be executed on the IoT device itself. The Fast Fourier Transformation (FFT) is used as an example for the arithmetic tasks to be supported. To support such specific applications, we envisage a concept for edge computing in which co-processing is implemented using Field Programmable Gate Arrays (fpgas). This article first describes certain edge computing requirements using the example of moving drones. This involves the case-by-case reconfiguration of the computation hardware and a handover mechanism from one edge node to another. Then follows the description of an FPGA-based FFT accelerator unit and its extension to an FFT co-processor. The development took place under the proviso that, for example, drones can request different co-processors and that the drones can also change the edge node when changing a radio cell, which results in a handover of the co-processor context. Regarding the FPGA part this means that the co-processor is part of a partially reconfigurable environment, and the co-processor must support the handover mechanisms in terms of hardware. Finally, the need for FPGA resources is analyzed, also in comparison with alternative solutions.

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Minimizing Area Footprint of UAV Communication Security Using fpgas

Minimizing Area Footprint of UAV Communication Security Usin...

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Cyber Security and Resilience (CSR), IEEE International conference on

作者： Evangelia Konstantopoulou George S. Athanasiou Nicolas Sklavos Computer Engineering & Informatics Dept. SCYTALE Group University of Patras Patras Hellas U-blox Athens S.A. Athens Hellas

ISBN: (数字)9798350375367

ISBN: (纸本)9798350375374

Nowadays, unmanned aerial vehicles (UAVs) are used in numerous applications, facilitating human activities. However, UAVs are vulnerable to cyberattacks, particularly concerning communication. To protect UAV communication, lightweight cryptographic algorithms have been enrolled, ensuring security in such resource-constrained environments. The National Institute of Standards and technology (NIST) promoted sponge constructions and nonlinear feedback shift registers (NFSR) as the bases for lightweight cryptography. As hardware offers significant advantages regarding performance and area-footprint over software, research moved on employing reconfigurable computing like Field-Programmable Gate Arrays (fpgas) in this field. This paper proposes a novel security realization in UAVs based on hardware implementation of lightweight NFSR-based authenticated encryption, targeting reduced-area and uncompromised security. Xilinx Artix-7 FPGA is considered and NIST lightweight finalist TinyJAMBU mechanism is employed. The area consumption of the proposed solution is minimal, compared to existing solutions in the literature, making it ideal for UAV devices with limited bandwidth and computational resources.

关键词： Software algorithms NIST Autonomous aerial vehicles Shift registers Hardware Software Encryption

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Efficient Architecture for a High Performance Authenticated Encryption Algorithm on reconfigurable computing 9th

Efficient Architecture for a High Performance Authenticate...

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9th EAI International conference on Advancement of Science and technology, ICAST 2021

作者： Abebe, Abiy Tadesse Shiferaw, Yalemzewd Negash Kumar, P. G. V. Suresh School of Electrical and Computer Engineering Addis Ababa Institute of Technology AAU Addis Ababa Ethiopia Ambo University Ambo Ethiopia

ISBN: (纸本)9783030937089

High performance authenticated encryption algorithms are indispensable and preferable for securing the contemporary high speed wireless networks as they can perform their tasks without affecting overall performance of the network, and can provide data confidentiality, data integrity, and authentication cryptographic services simultaneously. Most of existing FPGA based architectures that have been proposed to enhance performance of such algorithms considered generic FPGA fabrics for implementations. Implementing complex algorithms using only traditional FPGA logic requires large amount of such resources that in turn can affect performance. In this work, an efficient architecture for AEGIS-128 authenticated encryption algorithm is proposed using both fpgas’ embedded hard-cores such as digital signal processing slices and block random access memories that have not been fully exploited for such applications with balanced amount of generic logic. The aim is to reduce performance bottlenecks and enhance performance of AEGIS-128. The implementation results show that the proposed architecture outperforms existing similar approaches found in the literature in terms of throughput, and utilization of reduced amount of resources. © 2022, ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering.

关键词： Cryptography

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Area Efficient Hardware Architecture of Skeletonization for 2D Images 12

Area Efficient Hardware Architecture of Skeletonization for ...

引用

12th International conference on computing Communication and Networking Technologies, ICCCNT 2021

作者： Verma, Kajal Meenpal, T. Jaiswal, Kokila Bharti Dept. of Electronics & Comm. National Institute of Technology CG Raipur492010 India

ISBN: (纸本)9781728185958

Thinning algorithms (TA) are commonly utilized to extract an object's functioning parameters. The skeletonization algorithm (SA) comprises of broad range of complex mathematics and involves lengthy implementations when dealing with real time (RT). Algorithms on hardware platforms can be applied to boost the efficiency of image processing applications. reconfigurable equipment used as hardware module in the field of Field Programmable Gate Arrays (fpgas) that can offer high performance with lower latency are being used for real world applications. fpgas' inherent reprogramming capacity allows them application versatility while maintaining the efficiency benefits of a particular approach for an operation. Just real-time hardware devices can be used with fewer tools as in real-time implementations image sizes get larger. In the proposed architecture, the 8x8 image pixels are processed in one 3x3 window per clock cycle instead of one pixel per cycle. The proposed design shows significant reduction in area. © 2021 IEEE.

关键词： Pixels

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reconfigurable Distributed FPGA Cluster Design for Deep Learning Accelerators

Reconfigurable Distributed FPGA Cluster Design for Deep Lear...

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IEEE International conference on Electro-Information technology

作者： Hans Johnson Tianyang Fang Alejandro Perez-Vicente Jafar Saniie Department of Electrical and Computer Engineering Embedded Computing and Signal Processing (ECASP) Research Laboratory Illinois Institute of Technology Chicago IL U.S.A.

We propose a distributed system based on low-power embedded fpgas designed for edge computing applications focused on exploring distributing scheduling optimizations for Deep Learning (DL) workloads to obtain the best performance regarding latency and power efficiency. Our cluster was modular throughout the experiment, and we have implementations that consist of up to 12 Zynq-7020 chip-based boards as well as 5 UltraScale+ MPSoC FPGA boards connected through an ethernet switch, and the cluster will evaluate configurable Deep Learning Accelerator (DLA) Versatile Tensor Accelerator (VTA). This adaptable distributed architecture is distinguished by its capacity to evaluate and manage neural network workloads in numerous configurations which enables users to conduct multiple experiments tailored to their specific application needs. The proposed system can simultaneously execute diverse Neural Network (NN) models, arrange the computation graph in a pipeline structure, and manually allocate greater resources to the most computationally intensive layers of the NN graph.

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Weighing up the new kid on the block: Impressions of using Vitis for HPC software development 30

Weighing up the new kid on the block: Impressions of using V...

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30th International conference on Field-Programmable Logic and applications (FPL)

作者： Brown, Nick Univ Edinburgh Bayes Ctr EPCC 47 Potterrow Edinburgh EH8 9BT Midlothian Scotland

ISBN: (纸本)9781728199023

The use of reconfigurable computing, and fpgas in particular, has strong potential in the field of High Performance computing (HPC). However the traditionally high barrier to entry when it comes to programming this technology has, until now, precluded widespread adoption. To popularise reconfigurable computing with communities such as HPC, Xilinx have recently released the first version of Vitis, a platform aimed at making the programming of fpgas much more a question of software development rather than hardware design. However a key question is how well this technology fulfils the aim, and whether the tooling is mature enough such that software developers using fpgas to accelerate their codes is now a more realistic proposition, or whether it simply increases the convenience for existing experts. To examine this question we use the Himeno benchmark as a vehicle for exploring the Vitis platform for building, executing and optimising HPC codes, describing the different steps and potential pitfalls of the technology. The outcome of this exploration is a demonstration that, whilst Vitis is an excellent step forwards and significantly lowers the barrier to entry in developing codes for fpgas, it is not a silver bullet and an underlying understanding of dataflow style algorithmic design and appreciation of the architecture is still key to obtaining good performance on reconfigurable architectures.

关键词： fpgas reconfigurable computing Vitis Alveo Himeno benchmark

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ILP Based Mapping for Elastic CGRAs

ILP Based Mapping for Elastic CGRAs

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IEEE International conference on Embedded and Real-Time computing Systems and applications (RTCSA)

作者： Makoto Saito Takuya Kojima Hideki Takase Hiroshi Nakamura Graduate School of Information Science and Technology The University of Tokyo Tokyo Japan

In recent years, the emergence of deep learning and the need for big data analysis have created a demand for computers with high computational performance and energy efficiency. Since conventional ASICs and general-purpose CPUs cannot meet this requirement, domain-specific architectures that constrain applications are currently the focus of attention. Coarse-Grained reconfigurable Architecture (CGRA), one of the domain-specific architectures, is attracting attention because it is superior to CPUs and fpgas in terms of computational performance and power efficiency [1]. As depicted in Fig. 1, CGRA comprises a two-dimensional array of Processing Elements (PEs) and provides flexibility to change the instructions executed on the PEs and the connections between them, depending on the software being executed. On the other hand, the mapping problem for CGRA is an NP-complete problem, and there exist tradeoffs between solution accuracy and execution time. For real time applications, it is indispensable to shorten the mapping time. Thus, in this study, we propose an Integer Linear Programming (ILP) based mapping method for Elastic CGRA that aims to shorten mapping time while preserving solution accuracy. We have also implemented and preliminary evaluated the proposed method.

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FPGA-based single board computer for data acquisition and trigger of the Muon g-2 laser calibration system

FPGA-based single board computer for data acquisition and tr...

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IEEE Symposium on Nuclear Science (NSS/MIC)

作者： S. Mastroianni A. Anastasio A. Boiano P. Di Meo M. Iacovacci F. Marignetti G. Tortone INFN Naples Naples Italy Federico II University Naples Italy Cassino Univertity Cassino Cassino Italy

ISBN: (数字)9798350388152

ISBN: (纸本)9798350388169

Single Board Computers (SBCs), based on microprocessor component with several expanding ports ensuring full integration with sensors and peripherals, are mainly used in embedded applications to perform a specific task (i.e. slow control operation). The increasing of computing power and the use of reconfigurable fpgas on these modules guarantee a high level of flexibility and allow the execution of different extensive functions such as real-time signal processing, data collection and trigger *** this work, we present the hardware architecture and software platform of a custom general purpose SBC hosting an FPGA and an ARM-based processor, specifically designed to control and monitor the laser calibration system of the calorimeters for the Muon g-2 experiment. In particular, we describe its implementation, the system operation and the performance during six years of data taking (from 2018 to 2023) to contain the gain fluctuations of the calorimeter photodetectors at the 0.01% level.

关键词： Computers Temperature sensors Temperature measurement Temperature distribution Mesons Systems operation Software

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