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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

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A novel heuristic and provable bounds for reconfigurable architecture design

A novel heuristic and provable bounds for reconfigurable arc...

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14th Annual IEEE Symposium on Field-Programmable Custom computing Machines

作者： Smith, Alastair M. Constantinides, George A. Cheung, Peter Y. K. Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London SW7 2AZ England

ISBN: (纸本)0769526616

This paper is concerned with the application of formal optimisation methods to the design of mixed-granularity fpgas. In particular, we investigate the appropriate mix and floorplan of heterogeneous elements: multipliers, RAMS, and LUT-based logic, in order to maximise the performance of a set of DSP benchmark applications, given a fixed silicon budget. We extend our previous mathematical programming framework by proposing a novel set of heuristics, capable of providing upper bounds on the achievable reconfigurable-to-fixed-logic performance ratio. Our results provide, for the first time, quantifications of the optimal performance/area-enhancing capability of multipliers and RAM blocks within a system context, and indicate that only a minimal performance benefit can be achieved over Virtex ii by re-organising the device floorplan, when using optimal technology mapping.

关键词： Computer architecture

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A reconfigurable supercomputing library for accelerated parallel lagged-Fibonacci pseudorandom number generation

A reconfigurable supercomputing library for accelerated para...

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2006 ACM/IEEE conference on Supercomputing, SC'06

作者： Bi, Yu. Peterson, Gregory D Warren, G. Lee Harrison, Robert J.

ISBN: (纸本)0769527000

To help promote more widespread adoption of hardware acceleration in parallel scientific computing we present portable, flexible design components for pseudorandom number generation. Due to the success of the Scalable Parallel Random Number Generators (SPRNG) software library in stochastic computations (e.g., Monte Carlo simulations), we developed an efficient and portable hardware architecture fully compatible with SPRNG's Parallel Additive Lagged Fibonacci Generator (PALFG). Our general design produces identical results for all the parameter sets that SPRNG supports and yields high performance parallel random number generators, which can each generate 162 million 31 bit uniform random integers per second on Xilinx Virtex ii Pro fpgas. The friendly design interface makes it easy for users to integrate into their applications, particularly computational scientists unfamiliar with reconfigurable hardware. Due to its fast generation speed and friendly interface, this uniform random number generator is being targeted as an open core for parallel scientific computing. © 2006 IEEE.

关键词： Data structures

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8-bit CISC microprocessor core for teaching applications in the digital systems laboratory

8-bit CISC microprocessor core for teaching applications in ...

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3rd IEEE International conference on reconfigurable computing and fpgas

作者： Romero-Troncoso, R. de J. Ordaz-Moreno, A. Vite-Frias, J. A. Garcia-Perez, A. Univ Guanajuato Fac Ingn Mecan Elect & Electron FIMEE Tampico 912 Salamanca 36730 Spain

ISBN: (纸本)1424406897

Recent developments on programmable logic technology had promoted the microprocessor design task from big companies targeting the mass market to the every day designer as intellectual property (IP) cores toward the system on-a-chip (SOC) approach. This paper shows the VHDL IP 8-bit CISC microprocessor core development which is intended as an open core for teaching applications in the digital systems laboratory. The core is fully open and therefore, the user can have access to all internal signals as well as the opportunity to make changes to the structure itself which is very useful when lecturing microprocessor design. The main advantages of the present core, compared with commercially available equivalent cores, are that it is not vendor sensitive allowing its implementation in almost any FPGA family and being an open core, it can be fully monitored and modified to fit specific design constrains. Several tests were performed to the microprocessor core, including an embedded microcontroller with RAM, ROM and I/O capabilities. The present development includes a meta-assembler and linker to embed user programs in a ROM, which is automatically generated as a VHDL description.

关键词： microprocessor education digital systems laboratory

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REPLICA2Pro: Task relocation by bitstream manipulation in virtex-ii/Pro fpgas

REPLICA2Pro: Task relocation by bitstream manipulation in vi...

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3rd conference on computing Frontiers 2006, CF '06

作者： Kalte, Heiko Porrmann, Mario University of Western Australia School of Computer Science and Software Engineering 35 Stirling Highway Crawley WA 6009 Heinz Nixdorf Institute System and Circuit Technology University of Paderborn 33102 Paderborn Germany

ISBN: (纸本)1595933026

One vision of dynamic hardware reconfiguration is to deliver virtually unlimited hardware resources to a set of hardware tasks implementing arbitrary functions. By using partial reconfiguration, these tasks can be allocated and de-allocated on the reconfigurable architecture while others continue to operate. However, the exact placement of each task can only be determined during runtime according to the current resource allocation. This requires relocating each task from its original position after place and route to an area of available resources. The process of relocating tasks can result in a major time overhead. In order to solve this problem we have developed the REPLICA2Pro (Relocation per online Configuration Alteration in Virtex-2/-Pro) filter, which is capable of performing task relocations by manipulating the task's bitstream during the regular allocation process without any extra time overhead. The filter architecture, our reconfigurable system approach as well as our design flow and an experimental system setup are presented in this paper. Copyright 2006 ACM.

关键词： Field programmable gate arrays (FPGA)

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An efficient implementation of high-accuracy finite difference computing engine on fpgas

An efficient implementation of high-accuracy finite differen...

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17th IEEE International conference on Application-Specific Systems, Architectures and Processors

作者： He, Chuan Qin, Guan Lu, Mi Zhao, Wei Texas A&M Univ College Stn TX 77843 USA

ISBN: (纸本)0769526829

Finite Difference (FD) methods are the most prevalent numerical modelling algorithms for evaluating initial or boundary value problems in scientific and engineering applications. Unfortunately, simulating time evolutions for transient physical phenomenon is computationally demanding and data-intensive. In this paper, we introduce an efficient implementation of FD computing engine on FPGA-based reconfigurable computing (RC) platform. Instead of following the formal high-order FD expressions with standard IEEE-754 compliant floating-point arithmetic units, we propose a new class of optimized finite-accurate FD schemes, whose FD coefficients are optimized to be represented with only a few binary bits without deteriorating numerical accuracy criterions. Furthermore, in order to simplify the implementation of floating-point summations, we replace the conventional costly floating-point adder tree by a floating-point/fixed-point hybrid accumulator using group-alignment technology. The resulting fully-pipelined FD computing engine with finite accurate coefficients can provide us similar or even better worst case relative and absolute rounding errors than standard floating-point arithmetic, but consumes only a fraction of hardware resources. This new design can be easily applied to our previous work [1] [4] and result in a more efficient and compact implementation with much higher computational performance.

关键词： Field programmable gate arrays (FPGA)

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Hardware join Java: a unified hardware/software language for dynamic partial runtime reconfigurable computing applications

Hardware join Java: a unified hardware/software language for...

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IEEE International conference on Field-Programmable technology (FPT)

作者： David Kearney John Hopf Advanced Computing Research Centre University of South Australia Australia

reconfigurable computing is maturing rapidly as fpgas combining hard core processors and high density logic block arrays become widely available at low cost. Application developers have been developing algorithms that cross the hardware software divide for some years but will in addition want to express the dynamic reconfiguration of fpgas made available via an operating system for reconfigurable computing. Whilst there are many behavioural languages available for expressing reconfigurable computing applications very few of them are comprehensive enough to address simultaneously these two requirements. In this paper we present an experimental language based on Java which aims to achieve the twin goals of a transparent hardware software interface and an integrated expression of dynamic reconfiguration. Hardware join Java (HJJ) uses a common threading abstraction and synchronization based on the Join calculus to unify the semantics and interface between hardware and software. The language extends the dynamic class instantiation mechanism of Java (supported by the services of an operating system for reconfigurable computing) to express user initiated dynamic reconfiguration of the FPGA. In this paper we present basic syntax and semantics of HJJ and give our initial experience with the prototype compiler

关键词： Hardware Java Runtime Computer applications Application software Field programmable gate arrays Logic arrays Operating systems reconfigurable logic Costs

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The Learning of reconfigurable computing in the Computer Engineering Program

The Learning of Reconfigurable Computing in the Computer Eng...

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Frontiers in Education (FIE) conference

作者： Edson Pedro Ferlin Valfredo Pilla Computer Engineering Department Centro Universitário Positivo - UnicenP Curitiba PR Brazil Professor Computer Engineering Department Centro Universitário Positivo - UnicenP vpilla@unicenp.edu.br

The reconfigurable computing has an increasing importance in the computational solutions because of its two main characteristics: performance and flexibility. This became possible with the technological advance of the complex programmable logic devices (CPLDs) and the field programmable gate array (fpgas), which makes possible an increasing level of system integration (hardware and software). This integration can allow the construction of a complex system in a single device, the system on chip (SoC) technology. This is a multidisciplinary area, because it involves digital systems projects (some time analog systems also), firmware and operational systems development, beyond the specific knowledge of the areas of the systems applications. For this reasons the reconfigurable computation became part of the computer engineer formation. It is imperative that the new professionals have complete domain of this technology to be able to integrate it in the new computational systems. These computational systems reach a wide range of applications, from high performance computing to embedded systems, personal and mobile computing, to entertainment and mobile communication. In this direction, we present the evolution that happened in the Computer Engineering Program at UnicenP from the adoption of the technology of CPLDs and fpgas in several courses, and the inclusion of a specific reconfigurable computing course

关键词： Field programmable gate arrays High performance computing Programmable logic arrays Application software Embedded computing Programmable logic devices Field programmable analog arrays Hardware System-on-a-chip Digital systems

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The reconfigurable computing Applied to the Learning in the Computer Engineering Program

The Reconfigurable Computing Applied to the Learning in the ...

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International conference on Information technology Based Higher Education and Training, ITHET

作者： Valfredo Pilla Edson P. Ferlin Computer Engineering Department UnicenP-Centro Universitário Positivo Rua Prof Pedro Viriato Parigot de Souza 5300-Campo Comprido-Curitiba-PR Brazil E. P. Ferlin Chair Computer Engineering Department Centro Universitário Positivo - UnicenP Brazil

The reconfigurable computing has an increasing importance in the computational solutions because of its two mains characteristics: performance and flexibility. This became possible with the technological advance of the programmable logic devices (PLDs) and the field programmable gate array (fpgas), which makes possible an increasing level of system integration (hardware and software). This integration can allow the construction of a complex system in a single device, the system on chip (SoC) technology. This is a multidisciplinary area, because it involves digital systems projects (some time analog systems also), firmware and operational systems development, beyond the specific knowledge of the areas of the systems applications. For this reasons the reconfigurable computation became part of the computer engineer formation. It is imperative that the new professionals have complete domain of this technology to be able to integrate it in the new computational systems. These computational systems reach a wide range of applications, from high performance computing to embedded systems, personal and mobile computation, to entertainment and mobile communication. In this direction, we present the evolution that happened in the Computer Engineering Program at UnicenP from the adoption of the technology of PLDs and fpgas in several courses, and the inclusion of a specific course of reconfigurable computing.

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Exploring Non-Traditional Hardware-Software Interaction

Exploring Non-Traditional Hardware-Software Interaction

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Jorge A. Suris Peter Athanas Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg VA USA

The joint test action group (JTAG) has created what has become a world-wide standard/debug interface for a variety of hardware devices. The emergence of devices such as the Xilinx Virtex-ii Pro FPGA, which closely couple advanced microprocessors with reconfigurable logic, presents an opportunity to expand JTAG's capabilities beyond debugging. We present the design and implementation of a platform that combines JTAG, reconfigurable logic, and advanced processor debug features to create a rich environment for exploring non-traditional interaction between hardware and software. More specifically, we outline several possible configurations, discuss performance, and present possible applications

关键词： Hardware Debugging Communication system control Microprocessors Application software Runtime Process control Backplanes Circuit testing reconfigurable logic

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On reconfigurable Architectures for Efficient Matrix Inversion

On Reconfigurable Architectures for Efficient Matrix Inversi...

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International conference on Field Programmable Logic and applications

作者： Goncalo M. De Matos Horacio C. Neto INESC-ID / IST Technical University of Lisbon Portugal

This paper presents an analysis of the performance of the Gauss-Jordan matrix inversion algorithm on reconfigurable hardware platforms. The results show that currently available reconfigurable computing technology can already achieve significantly higher floating-point performance than CPUs for large matrices operations. For common reconfigurable systems, where the fpgas are directly coupled to the on-board memory, the achievable performance scales directly with the number of realizable simultaneous memory accesses. A dedicated reconfigware architecture has been implemented and tested on a standard commercial reconfigurable platform. Even though the platform used had limited data bandwidth between the FPGA and the on-board memory, speed improvements of more than 3times have been observed, in comparison with software solutions running in high-end CPUs, for the inversion of matrices of orders up to 1700

关键词： reconfigurable architectures Gaussian processes Field programmable gate arrays Performance analysis Matrices Algorithm design and analysis Hardware Computer architecture Power engineering computing Computer applications

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