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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

共 418 条记录，以下是301-310 订阅

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Robust Ultra-Low Power Subthreshold Logic Flip-Flop Design for reconfigurable Architectures

Robust Ultra-Low Power Subthreshold Logic Flip-Flop Design f...

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： Ameet Chavan Gaurav Dukle Ben Graniello Eric MacDonald Electrical and Computer Engineering University of Texas Paso Paso TX USA Intel Corporation Chandler AZ USA

Low power consumption and radiation hardness are generally competing requirements for space electronics as well as many Earth-bound high reliability applications. Fault tolerance typically requires redundancy and reconfigurability to ensure correct functional operation in the presence of errors. However, this runs contrary to the requirement for reduced power consumption in many battery-powered applications. Recently, subthreshold logic has emerged as a technology that delivers the theoretical minimum energy per computation by running at ultra-low voltages. For many applications, the resulting performance degradation is tolerable due the dramatic increase in energy efficiency. Beyond the concerns with performance, an additional challenge is related to radiation hardness and noise immunity. The marriage of subthreshold logic and reconfigurable, high-reliability electronics is inevitable, yet there has been to date no investigation of the effects of radiation on circuits that operate at such low voltages. This paper provides a comprehensive comparison of a variety of flip-flop designs at subthreshold levels

关键词： Robustness Logic design reconfigurable logic Flip-flops reconfigurable architectures Energy consumption Space technology Fault tolerance Redundancy Error correction

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Performance evaluations of ReconfigME

Performance evaluations of ReconfigME

引用

IEEE International conference on Field-Programmable technology (FPT)

作者： Grant Wigley David Kearney Reconfigurable Computing Laboratory University of South Australia Mawson Lakes SA Australia

With the development of reconfigurable computers containing fpgas with in excess of 6 million system-gates, it is now feasible to consider the possibility of sharing the FPGA between multiple concurrently executing applications. This could potentially increase the resource usage of the expensive FPGA logic and decrease response times so users will not have to wait for the FPGA to be completely available. However the system environment software required to support this, may actually result in application performance much less than would be considered acceptable to many FPGA users. This paper involves using a prototype to evaluate the performance of such an operating system, ReconfigME

关键词： Field programmable gate arrays Application software Concurrent computing reconfigurable logic Delay Software performance Software systems Software prototyping Prototypes Operating systems

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Virtex ii FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems

Virtex II FPGA Bitstream Manipulation: Application to Reconf...

引用

International conference on Field Programmable Logic and applications

作者： Y. E. Krasteva E. De La Torre T. Riesgo Didier Joly Grupo de Electr6nica Industrial Univ. Politecnica de Madrid Spain Memondo Graphics inc. Spain

This paper presents a tool for Virtex ii (Pro) FPGA partial bitstream manipulation suited for reconfigurable control systems with limited computing resources. The basics for partial bitstream manipulation in Virtex ii (Pro) fpgas are shown, including bit allocation equations that could be used to create such tools. After that, a tool for partial bitstream manipulation, called pBITPOS, and a use case in a reconfigurable control system are described. Differently from other non Virtex ii (Pro) solutions, this tool can be integrated in a reconfiguration control system, running on an embedded device, and it can handle BRAM/MULs related data.

关键词： Field programmable gate arrays Control systems Equations Java Logic Clocks Registers Electrical equipment industry Industrial control Bit rate

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reconfigurable accelerator for quantum Monte Carlo simulations in N-body systems

Reconfigurable accelerator for quantum Monte Carlo simulatio...

引用

2006 ACM/IEEE conference on Supercomputing, SC'06

作者： Gothandaraman, Akila Warren, G. Lee Peterson, Gregory D. Harrison, Robert J.

ISBN: (纸本)0769527000

Recent advances in FPGA technology make them an attractive platform for accelerating scientific computing applications. We present a novel hardware accelerator for Quantum Monte Carlo simulations in N-body systems. The design is deeply pipelined and exploits the inherent fine-grained parallelism available using an FPGA for all calculations. The design is implemented on a Xilinx Virtex ii Pro XC2VP30 device and preliminary results indicate a maximum operating frequency of 100MHz. A single instance of our design offers an estimated speedup of 20x and accuracy comparable to the serial code running on a 2.8GHz Intel Pentium 4 processor. This architecture performs all computations with fixed-point representation and delivers accuracy on the order of or better than double-precision floating point. After deploying a single instance on the present FPGA platform, targeting our design on the Cray XD1 platform with a high gate-density FPGA will allow us to operate multiple cores in parallel. © 2006 IEEE.

关键词： Field programmable gate arrays (FPGA)

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High Performance Power Spectrum Analysis Using a FPGA Based reconfigurable computing Platform

High Performance Power Spectrum Analysis Using a FPGA Based ...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Yogindra Abhyankar C Sajish Yogesh Agarwal C.R. Subrahmanya Peeyush Prasad Centre for Development of Advanced Computing Hardware Technology Development Group Pune India Department of Astronomy and Astrophysics Raman Research Institute Bangalore India Department of Astronomy and Astrophysics Raman Research Institute Raman Research Institute Bangalore India

Power-spectrum analysis is an important tool providing critical information about a signal. The range of applications includes communication-systems to DNA-sequencing. If there is interference present on a transmitted signal, it could be due to a natural cause or superimposed forcefully. In the later case, its early detection and analysis becomes important. In such situations having a small observation window, a quick look at power-spectrum can revel a great deal of information, including frequency and source of interference. In this paper, we present our design of a FPGA based reconfigurable platform for high performance power-spectrum analysis. This allows for the real-time data-acquisition and processing of samples of the incoming signal in a small time frame. The processing consists of computation of power, its average and peak, over a set of input values. This platform sustains simultaneous data streams on each of the four input channels

关键词： Performance analysis Field programmable gate arrays High performance computing Signal analysis Interference Frequency Signal processing Costs Hardware Information analysis

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Mapping Recursive Functions to reconfigurable Hardware

Mapping Recursive Functions to Reconfigurable Hardware

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International conference on Field Programmable Logic and applications

作者： George Ferizis Hossam El Gindy CSIRO ICT Centre Canberra ACT Australia School of Computer Science and Engineering University of New South Wales Sydney NSW Australia

reconfigurable computing devices such as fpgas offer application developers the ability to create solutions with a performance comparable to that of a hardware solution, but with the flexibility of software. Development tools that attempt to support popular software development languages such as C and Java have been developed to reduce the need for the FPGA developer to be trained in hardware design practices, however the tools have not been successful in mirroring all of the languages functionality. In particular most tools do not support programming with recursive functions. Previous research on mapping recursive functions to reconfigurable hardware has built a stack on the device which does not take full advantage of the massive amount of parallel resources on the reconfigurable device. This paper describes a method for mapping recursive functions to reconfigurable hardware without the use of a stack. It does this by unrolling the function on the device as it is executing. The results presented in this paper show that using this method can result in a significant performance increase when compared to a stack based implementation.

关键词： Hardware Field programmable gate arrays Space technology Parallel processing Pipeline processing Software packages Packaging Australia Computer science Software tools

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IRS - A Portable Interface for reconfigurable Systems

IRS - A Portable Interface for Reconfigurable Systems

引用

International conference on Parallel computing in Electrical Engineering (PARLEC)

作者： T. Mehlan J. Strunk T. Hoefler F. Mietke W. Rehm Chair of Computer Architecture Chemnitz University of Technology Germany

This work introduces the definition of a new interface for reconfigurable systems (IRS). Since modern fpgas support dynamic and partial reconfiguration, new core modules may be configured during normal operation. User applications are expected to benefit from the support of current FPGA hardware. To access this hardware there is a need for a well-defined interface. This paper proposes an application programming interface (API) that meets the requirements of fast hardware access, portability and ease of use. Moreover the work explains how to implement the services for a maximum of portability

关键词： Field programmable gate arrays Hardware User interfaces Operating systems Registers Computer architecture Chemical technology Application software Workstations Read-write memory

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A Novel Hueristic and Provable Bounds for reconfigurable Architecture Design

A Novel Hueristic and Provable Bounds for Reconfigurable Arc...

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Annual IEEE Symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Alastair M. Smith George A. Constantinides Peter Y. K. Cheung Department of Electrical and Electronic Engineering Imperial College London UK

This paper is concerned with the application of formal optimisation methods to the design of mixed-granularity fpgas. In particular, the authors investigate the appropriate mix and floorplan of heterogeneous elements: multipliers, RAMs, and LUT-based logic, in order to maximise the performance of a set of DSP benchmark applications, given a fixed silicon budget. The authors extend our previous mathematical programming framework by proposing a novel set of heuristics, capable of providing upper bounds on the achievable reconfigurable-to-fixed-logic performance ratio. The results provide, for the first time, quantifications of the optimal performance/area-enhancing capability of multipliers and RAM blocks within a system context, and indicate that only a minimal performance benefit can be achieved over Virtex ii by re-organising the device floorplan, when using optimal technology mapping

关键词： reconfigurable architectures Optimization methods Design methodology Field programmable gate arrays reconfigurable logic Logic programming Digital signal processing Silicon Mathematical programming Upper bound

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A Novel Heuristic and Provable Bounds for reconfigurable Architecture Design

A Novel Heuristic and Provable Bounds for Reconfigurable Arc...

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International conference on Field Programmable Logic and applications

作者： Alastair M. Smith George A. Constantinides Peter Y. K. Cheung Department of Electrical and Electronic Engineering Imperial College London UK

This paper is concerned with the application of formal optimisation methods to the design of mixed-granularity fpgas. In particular, we investigate the appropriate mix and floorplan of heterogeneous elements: multipliers, RAMs, and LUT-based logic, in order to maximise the performance of a set of DSP benchmark applications, given a fixed silicon budget. We extend our previous mathematical programming framework by proposing a novel set of heuristics, capable of providing upper-bounds on the achievable reconfigurable-to-fixed-logic performance ratio. Moreover, we use linear-programming bounding procedures from the operations research community to provide lower-bounds on the same quantity. Our results provide, for the first time, quantifications of the optimal performance/area-enhancing capability of multipliers and RAM blocks within a system context, and indicate that only a minimal performance benefit can be achieved over Virtex ii by re-organising the device floorplan, when using optimal technology mapping

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8-bit CISC Microprocessor Core for Teaching applications in the Digital Systems Laboratory

8-bit CISC Microprocessor Core for Teaching Applications in ...

引用

International conference on reconfigurable computing and fpgas (ReConFig)

作者： R.-T.R. de J A. Ordaz-Moreno J. A. Vite-frias A. Garcia-Perez Universidad de Guanajuato Guanajuato Guanajuato MX Facultad de Ingenieria Mecanica Electrica y Electronica Universidad de Guanajuato Salamanca Mexico

Recent developments on programmable logic technology had promoted the microprocessor design task from big companies targeting the mass market to the every day designer as intellectual property (IP) cores toward the system on-a-chip (SOC) approach. This paper shows the VHDL IP 8-bit CISC microprocessor core development which is intended as an open core for teaching applications in the digital systems laboratory. The core is fully open and therefore, the user can have access to all internal signals as well as the opportunity to make changes to the structure itself which is very useful when lecturing microprocessor design. The main advantages of the present core, compared with commercially available equivalent cores, are that it is not vendor sensitive allowing its implementation in almost any FPGA family and being an open core, it can be fully monitored and modified to fit specific design constrains. Several tests were performed to the microprocessor core, including an embedded microcontroller with RAM, ROM and I/O capabilities. The present development includes a meta-assembler and linker to embed user programs in a ROM, which is automatically generated as a VHDL description

关键词： Microprocessors Education Digital systems Laboratories Read only memory Logic design Programmable logic arrays Programmable logic devices Intellectual property Signal design

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