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International conference on Application Specific Systems (ASAP), Architectures and Processors

作者： Chuan He Guan Qin Mi Lu Wei Zhao Texas A and M University College Station TX USA

Finite difference (FD) methods are the most prevalent numerical modelling algorithms for evaluating initial or boundary value problems in scientific and engineering applications. Unfortunately, simulating time evolutions for transient physical phenomenon is computationally demanding and data-intensive. This paper introduces an efficient implementation of FD computing engine on FPGA-based reconfigurable computing (RC) platform. Instead of following the formal high-order FD expressions with standard IEEE-754 compliant floating point arithmetic units, a new class of optimized finite-accurate FD schemes was proposed, whose FD coefficients are optimized to be represented with only a few binary bits without deteriorating numerical accuracy criterions. Furthermore, in order to simplify the implementation of floating-point summations, the conventional costly floating-point adder tree was replaced by a floating-point/fixed-point hybrid accumulator using group-alignment technology. The resulting fully-pipelined FD computing engine with finite accurate coefficients can provide us similar or even better worst case relative and absolute rounding errors than standard floating-point arithmetic, but consumes only a fraction of hardware resources. This new design can be easily applied to our previous work (He et al., 2005) and result in a more efficient and compact implementation with higher computational performance

关键词： Finite difference methods Engines Field programmable gate arrays Floating-point arithmetic Numerical models Boundary value problems Computational modeling Physics computing Roundoff errors Hardware

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A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications 06

A reconfigurable HW/SW platform for computation intensive hi...

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Design, Automation and Test in Europe conference and Exhibition

作者： A. do Carmo Lucas S. Heithecker P. Ruffer R. Ernst H. Ruckert G. Wischermann K. Gebel R. Fach W. Huther S. Eichner G. Scheller Technical University of Braunschweig Germany Grass Valley Germany GmbH Thomson group Technical University Ilmenau Germany

ISBN: (纸本)9783981080100

This paper presents a multi-board, multi-FPGA hardware/software architecture, for computation intensive, high resolution (2048times2048pixels), real-time (24 frames per second) digital film processing. It is based on Xilinx Virtex-ii Pro fpgas, large SDRAM memories for multiple frame storage and a PCI express communication network. The architecture reaches record performance running a complex noise reduction algorithm including a 2.5 dimensions DWT and a full 16times16 motion estimation at 24 fps requiring a total of 203 Gops/s net computing performance and a total of 28 Gbit/s DDR-SDRAM frame memory bandwidth. To increase design productivity and yet achieve high clock rates (125MHz), the architecture combines macro component configuration and macro level floorplanning with weak programmability using distributed microcoding. As an example, the core of the bidirectional motion estimation using 2772 CLBs reaching 155 Gop/s (1538 op/pixel) requiring 7 Gbit/s external memory bandwidth was developed in two men-months

关键词： Computer architecture Motion estimation Bandwidth Application software Hardware Software architecture Field programmable gate arrays SDRAM Communication networks Noise reduction

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A system-level design methodology for reconfigurable computing applications

A system-level design methodology for reconfigurable computi...

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4th IEEE International conference on Field Programmable technology

作者： El-Araby, E El-Ghazawi, T Gaj, K George Washington Univ Washington DC 20052 USA

ISBN: (纸本)0780394070

reconfigurable Computers (RCs) can leverage the synergism between conventional processors and fpgas by combining the flexibility of traditional microprocessors with the parallelism of hardware and reconfigurability of fpgas. However, there exist multiple challenges that must be resolved to be able to develop efficient applications for reconfigurable computing systems. One of these challenges is the lack of formal modeling/design methodology. This work, addresses the need for a formal design methodology. In particular, a structured design life-cycle, which can be applied at the reconfigurable computing systems rather than at the chip-level as it has been traditionally the case, is conceptually proposed, formally modeled and experimentally verified.

关键词： Field programmable gate arrays (FPGA)

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Towards run-time partitioning of a real time operating system for reconfigurable systems on chip

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IFIP Advances in Information and Communication technology 2005年 184卷 255-266页

作者： Götz, Marcelo Rettberg, Achim Pereira, Carlos Eduardo Heinz Nixdorf Institute University of Paderborn Germany C-LAB University of Paderborn Germany Departamento de Engenharia Eletrica UFRGS - Universidade Federal do Rio Grande do Sul Brazil

ISBN: (纸本)9780387275574

reconfigurable computing have successfully been designed taking into advantage the supporting of architectures based on the fpgas and CPU. Moreover, the new hybrid fpgas (e.g. Virtex-ii Pro™), provides a hardcore general-purpose processor (GPP) embedded into a field of programmable gate arrays. Together with the ability to be partially reconfigured, those chips are very attractive for implementation of run-time reconfigurable embedded systems. However, most of the efforts in this field were made in order to apply these capabilities at application level, leaving to the Operating System (OS) the provision of the necessary mechanisms to support these applications. This paper present an approach for run-time reconfigurable Operating System, which take advantage of the new hybrid FPGA chips to reconfigure itself based on online estimation of application demands. The paper focus on run-time assignment and reconfiguration of OS services over a hybrid architecture. The proposed model uses a 0-1 Integer programming strategy for assigning OS components over a hybrid architecture, as well as an alternative heuristic algorithm for it. In addition, the evaluation of the reconfiguration costs are presented and discussed.

关键词： System-on-chip

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Micro-Task Processing in Heterogeneous reconfigurable Systems

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Journal of Computer Science & technology 2005年第5期20卷 624-634页

作者： Sebastian Wallner Department of Distributed Systems Technical University of Hamburg-Harburg Schwarzenbergstrasse 95 D-21073 Hambur9 Germany

New reconfigurable computing architectures are introduced to overcome some of the limitations of conventional microprocessors and fine-grained reconfigurable devices （e.g., fpgas）. One of the new promising architectures axe Configurable System-on-Chip （CSoC） solutions. They were designed to offer high computational performance for real-time signal processing and for a wide range of applications exhibiting high degrees of parallelism. The programming of such systems is an inherently challenging problem due to the lack of an programming model. This paper describes a novel heterogeneous system architecture for signal processing and data streaming applications. It offers high computational performance and a high degree of flexibility and adaptability by employing a micro Task Controller （mTC） unit in conjunction with programmable and configurable hardware. The hierarchically organized architecture provides a programming model, allows an efficient mapping of applications and is shown to be easy scalable to future VLSI technologies. Several mappings of commonly used digital signal processing algorithms for future telecommunication and multimedia systems and implementation results axe given for a standard-cell ASIC design realization in 0.18 micron 6-layer UMC CMOS technology.

关键词： system-on-chip reconfigurable heterogeneous architectures configuration instructions descriptors parallel processing system signal processing

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CHIADO - Compilation of high-level computationally intensive algorithms to dynamically reconfligurable computing systems

CHIADO - Compilation of high-level computationally intensive...

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conference on VLSI Circuits and Systems ii

作者： Cardoso, JMP Univ Algarve Fac Sci & Technol P-8000117 Faro Portugal

ISBN: (纸本)0819458325

reconfigurable computing has already confirmed a significant potential for accelerating certain computing tasks. However, the most successful applications relied on user expertise to design a specific architecture implemented by the hardware structures of the reconfigurable computing device. Hence, one of the most challenging issues is to map, efficiently and automatically, computations (described in software programming languages) to reconfigurable computing devices. This paper presents CHIADO, a research project aiming a compiler framework to map efficiently software programs to reconfigurable computing platforms, especially the ones based on FPGA (Field-Programmable Gate Array) devices. The framework is also intended to support research of new optimization techniques. The project, based on our previous work on compiling Java bytecodes to fpgas, focuses on high-performance solutions, schemes to estimate the impact of some transformations supported by the compiler (partial/full loop unrolling), and schemes to take advantage of dynamic reconfiguration (e.g., temporal partitioning). This paper gives an overview about the CHIADO project, shows the framework, and enumerates the main project goals.

关键词： compilation reconfigurable computing fpgas

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A design methodology to generate dynamically self-reconfigurable SoCs for Virtex-ii pro fpgas

A design methodology to generate dynamically self-reconfigur...

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4th IEEE International conference on Field Programmable technology

作者： Van den Branden, G Touhafi, A Dirkx, E Erasmushogesch Brussel IWT B-1070 Brussels Belgium

ISBN: (纸本)0780394070

Today, the technology is available for the creation of dynamically self-reconfigurable systems [1, 2]. However, the lack of efficient methodologies fir customizing the system to the requirements of the application withholds the widespread use of this promising technique. This paper fills the existing design productivity gap concerning dynamically self-reconfigurable Systems on Chip by proposing a consistent framework for the toolflow that will lead, in a very cost effective way, to an RT level implementation of this type of systems. As a proof of concept we discuss a case study where a virtual instrumentation machine for LISP applications is implemented on a Virtex-ii Pro component and where the reconfiguration process is controlled by an em bedded processor.

关键词： System-on-chip

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A run-time partitioning algorithm for RTOS on reconfigurable hardware

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International conference on Embedded and Ubiquitous computing, EUC 2005

ISBN: (纸本)3540308075

In today's system design, reconfigurable computing plays more and more an important role. By the extension of reconfigurable devices like fpgas with one or more CPUs new challenges in system design should be solved. These new hybrid fpgas (e.g. Virtex-ii Pro™), provides a hardcore general-purpose processor (GPP) embedded into a field of programmable gate arrays. Furthermore, they offer partial reconfiguration. Therefore, those hybrid fpgas are very attractive for implementation of run-time reconfigurable embedded systems. However, most of the efforts in this field were made in order to apply these capabilities at application level, leaving to the Operating System (OS) the provision of the necessary mechanisms to support these applications. In this paper, an approach for run-time reconfigurable Operating System, which takes advantage of the new hybrid fpgas to reconfigure itself based on online estimation of application demands, is presented. Especially run-time assignment and reconfiguration of OS services over hybrid architecture are discussed. The proposed model uses a 0-1 Integer programming strategy for assigning OS components over hybrid architecture, as well as an alternative heuristic algorithm for it. Furthermore, the evaluation of the reconfiguration costs are presented and discussed. © IFIP International Federation for Information Processing 2005.

关键词： Computer operating systems

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The design and application of a high-end reconfigurable computing system

The design and application of a high-end reconfigurable comp...

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2005 5th International conference on Engineering of reconfigurable Systems and Algorithms, ERSA'05

作者： Chang, Chen Wawrzynek, John Droz, Pierre-Yves Brodersen, Robert W. Department of Electrical Engineering and Computer Sciences University of California Berkeley United States

ISBN: (纸本)9781932415742

This paper summarizes our current effort in the BEE2 project to design and construct a high-end reconfigurable computer (HERC) system based solely on field programmable gate arrays (fpgas) as the processing elements. fpgas offer many important advantages over conventional microprocessors, such as flexible arithmetic precision, higher computational density per unit silicon area, and lower power consumption. The programmable interconnect structure unique to FPGA technology has made it possible to tailor a HERC system, such as the BEE2 system, on a per-problem basis to best take advantage of task specific data-flow, memory access patterns, and node-to-node communication patterns. The BEE2 project is a coordinated attack on the elements needed to demonstrate a practical, cost-effective, high-end reconfigurable computer: the design of a processing module to be used as the building block for a family of high-end reconfigurable computers;the development of several programming models;and the demonstration of the efficiency of the machine on a set of applications drawn from various research projects at Berkeley Wireless Research Center (BWRC), ranging from high-performance DSP and communication systems to traditional scientific computing. Preliminary analyses show that on selected DSP applications, when compared to a microprocessor-based system with similar power consumption and cost, BEE2 can provide over 10 times more computational efficiency.

关键词： Computational efficiency

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Micro-task processing in heterogeneous reconfigurable systems

Micro-task processing in heterogeneous reconfigurable system...

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9th Asia-Pacific Computer Systems Architecture conference (ACSAC 2004)

作者： Wallner, S Tech Univ Hamburg Dept Distributed Syst D-21073 Hamburg Germany

New reconfigurable computing architectures are introduced to overcome some of the limitations of conventional microprocessors and fine-grained reconfigurable devices (e.g., fpgas). One of the new promising architectures are Configurable System-on-Chip (CSoC) solutions. They were designed to offer high computational performance for real-time signal processing and for a wide range of applications exhibiting high degrees of parallelism. The programming of such systems is an inherently challenging problem due to the lack of an programming model. This paper describes a novel heterogeneous system architecture for signal processing and data streaming applications. It offers high computational performance and a high degree of flexibility and adaptability by employing a micro Task Controller (mTC) unit in conjunction with programmable and configurable hardware. The hierarchically organized architecture provides a programming model, allows an efficient mapping of applications and is shown to be easy scalable to future VLSI technologies. Several mappings of commonly used digital signal processing algorithms for future telecommunication and multimedia systems and implementation results are given for a standard-cell ASIC design realization in 0.18 micron 6-layer UMC CMOS technology.

关键词： system-on-chip reconfigurable heterogeneous architectures configuration instructions descriptors parallel processing system signal processing

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