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Towards a reconfigurable tracking system

Towards a reconfigurable tracking system

引用

2005 International conference on Field Programmable Logic and applications, FPL

作者： Wong, Sebastien C. Jasiunas, Mark Kearney, David Electronic Warfare and Radar Division Defence Science and Technology Organisation Australia PO Box 1500 Edinburgh SA 5111 Australia Advanced Computing Research Centre University of South Australia Mawson Lakes Campus Mawson Lakes SA 5095 Australia

ISBN: (纸本)0780393627

Robust real-time automatic detection tracking and classification of objects in imagery is one of the most computationally demanding tasks in computer vision. Historically the field of computer vision has been limited by computing power. In particular algorithms that require multiple correlations, convolutions and other complex operations can be prohibitive to implement on a microprocessor. Part of the poor performance of microprocessors is their serial nature, while many of these operations are inherently parallel. One approach to implementing these operations in parallel is to build them in hardware using application specific integrated circuits (ASIC). Another approach is to use Field Programmable Gate Arrays (fpgas) and reconfigurable computing. reconfigurable computing offers a trade-off between the speed of hardware and flexibility of software. This paper describes two computationally intensive tracking algorithms, investigates their implementation on a reconfigurable computer, and benchmarks their performance. From our preliminary results we find that reconfigurable computing is well suited to the implementation of real-time tracking systems. © 2005 IEEE.

关键词： Imaging systems

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Two-stage reconfigurable computing system architecture

Two-stage reconfigurable computing system architecture

引用

18th International conference on Systems Engineering, ICSEng 2005

作者： Deng, Yan-Xiang Hwang, Chao-Jang Lou, Der-Chyuan Dept. of Computer Sci. and Eng. Yuan Ze University Chungli Taoyuan 320 Taiwan Dept. of Electrical Eng. Chung Cheng Institute of Technology National Defense University Tahsi Taoyuan 335 Taiwan

ISBN: (纸本)0769523595

There are many successful applications of reconfigurable computing architecture in the past decade. They can be implemented into reconfigurable computing system according to their function algorithms usually. But, due to the influence of Gordon Moore's Law on FPGA (field programmable gate arrays) structure, the gate array sizes have been expanded widely under the technology of ULSI (ultra large scale integration). So, Using fpgas to implement the design of function level is waste of reconfigurable units. Therefore, how to build a powerful reconfigurable computing architecture is an important research topic. In this article, a new reconfigurable computing architecture named TSRCS (two-stage reconfigurable computing system) is proposed. The concept of TSRCS is to split the reconfiguration into two stages, one is SSR (system-stage reconfiguration) and another is FSR (function-stage reconfiguration). The SSR dynamically rebuilds routing networks that connect between RFBs (reconfigurable function blocks) but the FSR busily reconfigures RFBs following some computing algorithm that we want to do. The TSRCS can dynamic change not only the system architecture but also any function. The advantages of using TSRCS to implement a system are architecture flexible, function varied, system opening and performance changeable but the disadvantage is construction longer. In this paper, a new design method is proposed which can combine the forte of software and hardware to build a new system architecture and the research results have important contribution to computer science. © 2005 IEEE.

关键词： Computer architecture

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Design tradeoffs for BLAS operations on reconfigurable hardware

Design tradeoffs for BLAS operations on reconfigurable hardw...

引用

2005 International conference on Parallel Processing

作者： Zhuo, Ling Prasanna, Viktor K. Department of Electrical Engineering University of Southern California Los Angeles CA 90089-2562 United States

ISBN: (纸本)0769523803

Numerical linear algebra operations are key primitives in scientific computing. Performance optimizations of such operations have been extensively investigated and some basic operations have been implemented as software libraries. With the rapid advances in technology, hardware acceleration of linear algebra applications using fpgas (Field Programmable Gate Arrays) has become feasible. In this paper, we propose FPGA-based designs for several BLAS operations, including vector product, matrix-vector multiply, and matrix multiply. By identifying the design parameters for each BLAS operation, we analyze the design tradeoffs. In the implementations of the designs, the values of the design parameters are determined according to the hardware constraints, such as the available area, the size of on-chip memory, the external memory bandwidth and the number of I/O pins. The proposed designs are implemented on a Xilinx Virtex-ii Pro FPGA. © 2005 IEEE.

关键词： Computer hardware

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FPGA implementation of sparse matrix algorithm for information retrieval

FPGA implementation of sparse matrix algorithm for informati...

引用

conference on VLSI Circuits and Systems ii

作者： Bojanic, S Jevtic, R Nieto-Taladriz, O Univ Politecn Madrid ETSIT E-28040 Madrid Spain

ISBN: (纸本)0819458325

Information text data retrieval requires a tremendous amount of processing time because of the size of the data and the complexity of information retrieval algorithms. In this paper the solution to this problem is proposed via hardware supported information retrieval algorithms. reconfigurable computing may adopt frequent hardware modifications through its tailorable hardware and exploits parallelism for a given application through reconfigurable and flexible hardware units. The degree of the parallelism can be tuned for data. In this work we implemented standard BLAS (basic linear algebra subprogram) sparse matrix algorithm named Compressed Sparse Row (CSR) that is showed to be more efficient in terms of storage space requirement and query-processing timing over the other sparse matrix algorithms for information retrieval application. Although inverted index algorithm is treated as the de facto standard for information retrieval for years, an alternative approach to store the index of text collection in a sparse matrix structure gains more attention. This approach performs query processing using sparse matrix-vector multiplication and due to parallelization achieves a substantial efficiency over the sequential inverted index. The parallel implementations of information retrieval kernel are presented in this work targeting the Virtex 11 Field Programmable Gate Arrays (fpgas) board from Xilinx. A recent development in scientific applications is the use of FPGA to achieve high performance results. Computational results are compared to implementations on other platforms. The design achieves a high level of parallelism for the overall function while retaining highly optimised hardware within processing unit.

关键词： FPGA information retrieval sparse matrix multiplication high performance computing CSR algorithm

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A system-level design methodology for reconfigurable computing applications

A system-level design methodology for reconfigurable computi...

引用

IEEE International conference on Field-Programmable technology (FPT)

作者： E. El-Araby T. El-Ghazawi K. Gaj George Washington University USA George Mason University USA

reconfigurable computers (RCs) can leverage the synergism between conventional processors and fpgas by combining the flexibility of traditional microprocessors with the parallelism of hardware and reconfigurability of fpgas. However, there exist multiple challenges that must be resolved to be able to develop efficient applications for reconfigurable computing systems. One of these challenges is the lack of formal modeling/design methodology. This work, addresses the need for a formal design methodology. In particular, a structured design life-cycle, which can be applied at the reconfigurable computing systems rather than at the chip-level as it has been traditionally the case, is conceptually proposed, formally modeled and experimentally verified.

关键词： System-level design Computer applications Computer architecture Application software Design methodology Concurrent computing Field programmable gate arrays Parallel processing Space exploration Throughput

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Towards a reconfigurable tracking system

Towards a reconfigurable tracking system

引用

International conference on Field Programmable Logic and applications

作者： Sebastien C. Wong Mark Jasiunas David Kearney Electronic Warfare & Radar Division Defence Science and Technology Organisation Edinburgh SA Australia Advanced Computing Research Centre University of South Australia Mawson Lakes SA Australia

关键词： Computer vision Australia Object detection Layout Field programmable gate arrays Radar tracking Lakes Microprocessors Hardware Image recognition

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Two-stage reconfigurable computing system architecture

Two-stage reconfigurable computing system architecture

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IEEE International conference on Systems Engineering

作者： Yan-Xiang Deng Chao-Jang Hwang Der-Chyuan Lou Department of Computer Science and Engineering Yuan-Ze University Taoyuan Taiwan Department of Electrical Engineering Chung ChEngineering Institute of Technology National Defense University Taoyuan Taiwan

There are many successful applications of reconfigurable computing architecture. They can be implemented into reconfigurable computing system according to their function algorithms usually. But, due to the influence of Gordon Moore's Law on FPGA (field programmable gate arrays) structure, the gate array sizes have been expanded widely under the technology of VLSI (ultra large scale integration). So, Using fpgas to implement the design of function level is waste of reconfigurable units. Therefore, how to build a powerful reconfigurable computing architecture is an important research topic. In this article, a new reconfigurable computing architecture named TSRCS (two-stage reconfigurable computing system) is proposed. The concept of TSRCS is to split the reconfiguration into two stages, one is SSR (system-stage reconfiguration) and another is FSR (function-stage reconfiguration). The SSR dynamically rebuilds routing networks that connect between RFBs (reconfigurable function blocks) but the FSR busily reconfigures RFBs following some computing algorithm that we want to do. The TSRCS can dynamic change not only the system architecture but also any function. The advantages of using TSRCS to implement a system are flexible architecture, varied functions, open system, and changeable performance but the disadvantage is longer construction. In this paper, a new design method is proposed which can combine the forte of software and hardware to build a new system architecture and the research results have important contribution to computer science.

关键词： Computer architecture Field programmable gate arrays Computer applications Moore's Law Very large scale integration Ultra large scale integration Routing Computer networks Open systems Design methodology

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A design methodology to generate dynamically self-reconfigurable SoCs for Virtex-ii Pro fpgas

A design methodology to generate dynamically self-reconfigur...

引用

IEEE International conference on Field-Programmable technology (FPT)

作者： G. Van den Branden A. Touhafi E. Dirkx Brussel/IWT Erasmushogeschool Brussel Brussels Belgium Brussel/ETRO Vrije Universiteit Brussel Elsene Belgium

Today, the technology is available for the creation of dynamically self-reconfigurable systems. However, the lack of efficient methodologies for customizing the system to the requirements of the application withholds the widespread use of this promising technique. This paper fills the existing design productivity gap concerning dynamically self-reconfigurable systems on chip by proposing a consistent framework for the toolflow that will lead, in a very cost effective way, to an RT level implementation of this type of systems. As a proof of concept we discuss a case study where a virtual instrumentation machine for DSP applications is implemented on a Virtex-ii Pro component and where the reconfiguration process is controlled by an embedded processor

关键词： Design methodology Field programmable gate arrays Phased arrays Productivity System-on-a-chip Circuits Costs Instruments Digital signal processing chips Process control

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Design tradeoffs for BLAS operations on reconfigurable hardware

Design tradeoffs for BLAS operations on reconfigurable hardw...

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International conference on Parallel Processing (ICPP)

作者： L. Zhuo V.K. Prasanna Department of Electrical Engineering University of Southern California Los Angeles CA USA

Numerical linear algebra operations are key primitives in scientific computing. Performance optimizations of such operations have been extensively investigated and some basic operations have been implemented as software libraries. With the rapid advances in technology, hardware acceleration of linear algebra applications using fpgas (field programmable gate arrays) has become feasible. In this paper, we propose FPGA-based designs for several BLAS operations, including vector product, matrix-vector multiply, and matrix multiply. By identifying the design parameters for each BLAS operation, we analyze the design tradeoffs. In the implementations of the designs, the values of the design parameters are determined according to the hardware constraints, such as the available area, the size of on-chip memory, the external memory bandwidth and the number of I/O pins. The proposed designs are implemented on a Xilinx Virtex-ii Pro FPGA.

关键词： Hardware Field programmable gate arrays Linear algebra Scientific computing Optimization Software libraries Acceleration Application software Vectors Bandwidth

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reconfigurable hardware for addition chains based modular exponentiation

Reconfigurable hardware for addition chains based modular ex...

引用

International conference on Information technology: Coding and computing (ITCC)

作者： L. de Macedo Mourelle N. Nedjah Department of Systems Engineering and Computation State University of Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering State University of Rio de Janeiro Brazil

In several public-key cryptosystems, the main operation consists of the modular exponentiation, which is performed using successive modular multiplications. The size of the operands that are used in these cryptosystems is considerably large (1024 bits), consuming a considerable amount of time. This impacts on the performance of the cryptosystem, especially in real time applications. In order to reduce the execution time in these cryptosystems, the total number of modular multiplications must be reduced. There are several methods that attempt to reduce this number either by partitioning the exponent in windows or by reducing the number of elements to be multiplied. In this paper, we propose a fast and compact reconfigurable hardware for computing modular exponentiation using the addition-chain methods.

关键词： Hardware Elliptic curve cryptography Public key cryptography Partitioning algorithms Systems engineering and theory Telecommunication computing Elliptic curves Computer architecture Information technology

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