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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

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Prototyping automatic cloud cover assessment (ACCA) algorithm for remote sensing on-board processing on a reconfigurable computer

Prototyping automatic cloud cover assessment (ACCA) algorith...

引用

IEEE International conference on Field-Programmable technology (FPT)

作者： E. El-Araby M. Taher T. El-Ghazawi J. Le Moigne George Washington University USA NASA''s Goddard Space Flight Center USA

Clouds have a critical role in many studies, e.g. weather- and climate-related studies. However, they represent a source of errors in many applications, and the presence of cloud contamination can hinder the use of satellite data. This requires a cloud detection process to mask out cloudy pixels from further processing. The trend for remote sensing satellite missions has always been towards smaller size, lower cost, more flexibility, and higher computational power. reconfigurable computers (RCs) combine the flexibility of traditional microprocessors with the power of field programmable gate arrays (fpgas). Therefore, RCs are a promising candidate for on-board preprocessing. This paper presents the design and implementation of an RC-based real-time cloud detection system. We investigate the potential of using RCs for on-board preprocessing by prototyping the Landsat 7 ETM+ ACCA algorithm on one of the state-of-the art reconfigurable platforms, SRC-6E. Although a reasonable amount of investigations of the ACCA cloud detection algorithm using fpgas has been reported in the literature, very few details/results were provided and/or limited contributions were accomplished. Our work has been proven to provide higher performance and higher detection accuracy

关键词： Prototypes Remote sensing Cloud computing Satellites Field programmable gate arrays Computer errors Application software Contamination Costs Microprocessors

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CERPID: a reconfigurable platform interface driver for Windows ***

CERPID: a reconfigurable platform interface driver for Windo...

引用

ITI International conference on Information and Communications technology (ICICT)

作者： Z.M. Alassaad M.A.R. Saghir Department of Electrical and Computer Engineering American University of Beirut Lebanon

With the proliferation of computationally demanding embedded applications and the emergence of reconfigurable hardware devices, embedded systems would soon be designed around hybrid computational platforms consisting of a general-purpose processor and a reconfigurable logic unit. Such units can be reconfigured, often on the fly, to enhance the execution performance of various embedded applications. Microsoft's Windows CE is among the most widely used operating systems in embedded systems. However, its capabilities must be extended to support such hybrid computational platforms. In this paper we describe CERPID, a new class of device driver designed to manage hybrid computational platforms running under Windows CE. CERPID is a dynamic link library based on the Windows CE stream interface model. It consists of a layered architecture that abstracts the complexity of the operating system and provides an easy-to-use API for high-level language programmers to use the reconfigurable hardware. To demonstrate the functionality of CERPID, we develop a test application that we try on the XSA-50 Spartan-ii FPGA Board from Xess Corporation

关键词： Embedded computing Hardware Embedded system Operating systems Computer applications reconfigurable logic Computer interfaces Libraries Computer architecture Abstracts

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An Approach to Task Allocation for Dynamic Scheduling in reconfigurable computing Systems

An Approach to Task Allocation for Dynamic Scheduling in Rec...

引用

IEEE International conference on Multi Topic

作者： M. Ashraf Chughtai Arjumand Yaqoob Embedded Systems Design Group University of Engineering and Technology Lahore Pakistan

Recent research has expanded to encompass a view of the reconfigurable logic where a resource is shared among multiple applications or users. Runtime reconfiguration is a method of computing by dynamically changing hardware configurations from phase to phase of a computation. In real-time multitasking system design, task deadlines play an important role as systems not only need to support sharing of the resources in space, but also need to guarantee execution of the tasks. At the operating system level, sharing logic gates, wires, and I/O pins among multiple tasks needs to be managed; and, from the high level standpoint, access to the resources needs to be scheduled according to task deadlines. This paper describes a novel approach, based on hardware/software co-design modeling, to task allocation for scheduling tasks on a shared hardware under run-time constraints. The proposed task allocation technique has been implemented on a reconfigurable computing platform from Xilinx reg that employs Virtex-ii pro trade FPGA and embedded power PC core

关键词： Dynamic scheduling Hardware Runtime Processor scheduling reconfigurable logic Real time systems Multitasking Operating systems Logic gates Wires

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Have GPUs made fpgas redundant in the field of video processing?

Have GPUs made FPGAs redundant in the field of video process...

引用

IEEE International conference on Field-Programmable technology (FPT)

作者： B. Cope P.Y.K. Cheung W. Luk S. Witt Department of Electrical & Electronic Engineering Imperial College London London UK Department of Computing Imperial College London London UK Sony Broadcast and Professional USA

Since the 1990s fpgas have been popular for accelerating video processing applications. This paper presents GPUs (graphics processing units) as another viable solution, comparing their throughput with that of fpgas. Previous work on using fpgas and GPUs for video processing is analysed, grounds for comparison formulated and then exemplified through case studies of primary colour correction and 2D convolution. GPUs are seen to be advantageous in applications utilising their optimised instruction set and which have a low number of memory accesses. We found that for 2D convolution, the throughput of the GPUs exceeds that of fpgas if the mask dimension is 2 times 2. For mask sizes greater than 4 times 4 and for primary colour correction fpgas have higher throughput. The GPU implementation of primary colour correction is shown to be capable of a throughput of 63 MP/s (million pixels per second) enough for high definition video at 30 f/s (frames per second). For 2D convolution GPUs achieved the target throughput rate of 8MP/s (512 times 512 frames at 30 f/s) up to size 7 times 7. The Spartan 3 FPGA was capable of over 60 MP/s throughput and the Virtex ii Pro over 110 MP/s at this size of convolution

关键词： Field programmable gate arrays Throughput Parallel processing Convolution Color Pipeline processing Educational institutions Acceleration Graphics Application software

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A custom instruction approach for hardware and software implementations of finite field arithmetic over F/sub 2163/ using Gaussian normal bases

A custom instruction approach for hardware and software impl...

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IEEE International conference on Field-Programmable technology (FPT)

作者： M. Juliato G. Araujo J. Lopez R. Dahab Institute of Computing State University of Campinas-UNICAMP Sao Paulo Brazil

In this paper we explore the potential use of custom instructions in a reconfigurable hardware platform to accelerate arithmetic operations in the binary field F/sub 2163/ using a Gaussian normal basis representation. System-on-chip (SOC) techniques based on field programmable gate arrays (fpgas) are used, making it possible to run real applications on the system while considering all execution overheads. Thus we are able to fairly compare hardware and software performances, as well as precisely determine their speedups. Using this approach, we show that a field multiplication can be accelerated over 2619 times when implemented in hardware. Moreover, using this fast field multiplier in a hardware/software approach, we accelerate point multiplication, the fundamental operation of ECC, over 116 times.

关键词： Gaussian processes Hardware Galois fields Arithmetic Elliptic curve cryptography Field programmable gate arrays Acceleration Polynomials Application software Security

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Low leakage circuit design for fpgas

Low leakage circuit design for FPGAs

引用

IEEE Custom Integrated Circuits conference

作者： Ciccarelli, L Lodi, A Canegallo, R Univ Bologna ARCES I-40126 Bologna Italy

ISBN: (纸本)0780384954

reconfigurable computing is well suited for wireless applications because of their capability to adapt to changing communication protocols. However as technology scales fpgas could suffer from leakage energy consumption due to the large number of inactive transistors. This paper presents different buffered switches mixing low and high threshold transistors which trade some delay performance to reduce by two order of magnitude the leakage current of switch blocks which generate most of the dissipation in fpgas.

关键词： field programmable gate arrays leakage currents integrated circuit design logic design low-power electronics buffer circuits power consumption/propagation delay trade-off low leakage circuit design FPGA scaling reconfigurable computing communication protocols inactive transistor leakage energy consumption buffered switches mixed low/high threshold transistors

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HERA: A reconfigurable and mixed-mode parallel computing engine on platform fpgas

HERA: A reconfigurable and mixed-mode parallel computing eng...

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Proceedings of the 16th IASTED International conference on Parallel and Distributed computing and Systems

作者： Wang, Xiaofang Ziavras, Sotirios G. Department of Electrical Engineering New Jersey Institute of Technology Newark NJ 07102 United States

The high price, long design and development cycles, programming difficulty and high maintenance cost of supercomputers limit their range of potential applications. Recent advances in Field-Programmable Gate Arrays (fpgas) have made feasible the development of high-performance and programmable parallel systems on a programmable chip (PSOPC). PSOPC's yield high-performance at low cost for many parallel applications. We present in this paper the design and implementation of our HERA (HEterogeneous reconfigurable Architecture) machine that employs fpgas to allow the simultaneous execution of a variety of parallel processing modes, including SIMD (Single-Instruction, Multiple-Data), MIMD (Multiple-Instruction, Multiple-Data) and M-SIMD (Multiple-SIMD). The processing element is centered on a single-precision IEEE 754 floating-point unit (FPU) and employs a 7-stage pipeline. To demonstrate the robustness and viability of our approach, we propose a data partitioning scheme and employ mixed-mode scheduling for Cannon's matrix-matrix multiplication algorithm with matrices of arbitrary size and shape. Performance results on our 64-PE machine that employs a dual-FPGA system are better than the optimized performance on a dual-Xeon PC.

关键词： Parallel processing systems

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computing lennard-jones potentials and forces with reconfigurable hardware

Computing lennard-jones potentials and forces with reconfigu...

引用

Proceedings of the International conference on Engineering of reconfigurable Systems and Algorithms, ERSA'04

作者： Scrofano, Ronald Prasanna, Viktor K. Department of Computer Science University of Southern California Los Angeles CA Dept. of Elec. Engineering-Systems University of Southern California Los Angeles CA

ISBN: (纸本)1932415424

Technological advances have made fpgas an attractive platform for the acceleration of complex scientific applications. These applications demand high performance and high-precision floating point arithmetic. In this paper, we present a design for calculating the Lennard-Jones potential and force as is done in molecular dynamics simulations. This architecture employs IEEE 754 double precision floating point units, including a square root unit developed for this kernel. The design presented is a modular, very deeply pipelined architecture that exploits the fine-grained parallelism of the calculations. With the Xilinx Virtex-ii Pro as a target device, an implementation using two pipelines operating in parallel achieves 3.9 GFLOPS.

关键词： Field programmable gate arrays

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A high performance reconfigurable implementation of DES-like algorithms

A high performance reconfigurable implementation of DES-like...

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16th International conference on Microelectronics, ICM 2004

作者： Valizadeh, A. Zamani, M. Saheb Sadeghian, B. Mehdipour, F. Najafi, B. Department of Computer Engineering and IT Amirkabir University of Technology P.O. Box: 15875-4413 Tehran Iran

reconfigurable computing has grown to become an important and large field of research. It offers advantages over traditional hardware and software implementation of computational algorithms. It is based on using Field Programmable Gate Arrays (fpgas), which can be configured after fabrication to take advantage of a hardware design but still maintain the flexibility of software. Particular applications, including encryption, which involve repetitive computation, and have inherent parallelism, are specifically well suited to the use of fpgas. In this paper, We implemented four DES-like algorithms namely DES, DESX, Biham-DES, and Sn DES on a reconfigurable hardware so that each algorithm could be replaced by another with low reconfiguration overhead time. This kind of implementation not only has high flexibility but also has an acceptable encryption rate compared with the fastest implementation of DES. © 2004 IEEE.

关键词： Algorithms

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Implementing graphics shaders using fpgas 14th

Implementing graphics shaders using FPGAs

引用

14th International conference on Field Programmable Logic and applications, FPL 2004

作者： Thomas, David B. Luk, Wayne Department of Computing Imperial College LondonSW7 2BZ United Kingdom

ISBN: (纸本)3540229892

There are many similarities between modern 3D graphics chips and fpgas: a shader based graphic chip can be viewed as a highly domain specific and very coarse-grained reconfigurable logic device. Our goal is to see how a finegrained FPGA can be used to implement the pixel and vertex shader stages of a graphics pipeline, and how well the two methods compare in terms of speed, power, flexibility, and usability, initially by implementing Direct-X 9 pixel shader programs using Xilinx Virtex-ii fpgas.

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