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共 419 条记录，以下是341-350 订阅

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Implementing graphics shaders using fpgas 14th

Implementing graphics shaders using FPGAs

引用

14th International conference on Field Programmable Logic and applications, FPL 2004

作者： Thomas, David B. Luk, Wayne Department of Computing Imperial College LondonSW7 2BZ United Kingdom

ISBN: (纸本)3540229892

There are many similarities between modern 3D graphics chips and fpgas: a shader based graphic chip can be viewed as a highly domain specific and very coarse-grained reconfigurable logic device. Our goal is to see how a finegrained FPGA can be used to implement the pixel and vertex shader stages of a graphics pipeline, and how well the two methods compare in terms of speed, power, flexibility, and usability, initially by implementing Direct-X 9 pixel shader programs using Xilinx Virtex-ii fpgas.

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RECAST - Design space exploration for dynamic and reconfigurable embedded computing

RECAST - Design space exploration for dynamic and reconfigur...

引用

Proceedings of the International conference on Embedded Systems and applications ESA'04 - Proceedings of the International conference on VLSI, VLSI'04

作者： Preußer, Thomas B. Köhler, Steffen Spallek, Rainer G. Department of Computer Science Dresden University of Technology Dresden Germany

ISBN: (纸本)1932415416

The embedded computing domain has developed an increasing demand for programmable and reconfigurable processing solutions. As hardware cost, power consumption and performance are vital for the success of a solution, the functional and structural flexibility of available or newly-designed architectures must be carefully evaluated. This paper presents a framework for modelling and simulating dynamically reconfigurable architectures. An architecture description language will be proposed, which supports the modelling of dynamically reconfigurable architectures and serves the retargation of the framework. The introduced simulator is suited for design space exploration as well as hardware/software co-debugging. Both have been verified with models of the MIPS-ii and ARM7v4 architectures.

关键词： Embedded systems

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Pipelining designs with loop-carried dependencies

Pipelining designs with loop-carried dependencies

引用

2004 IEEE International conference on Field-Programmable technology, FPT '04

作者： Styles, Henry Thomas, David Barrie Luk, Wayne Department of Computing Imperial College 180 Queen's Gate London SW7 2BZ United Kingdom

ISBN: (纸本)0780386515

This paper explores the reconfigurable Dataflow approach in producing efficient hardware pipelines for programs with loop-carry dependencies in nested loops. reconfigurable Dataflow combines static and dynamic scheduling, and employs tagged tokens to enable re-assembling of results which can retire out of order. The effectiveness of this approach is illustrated using a fractal set generator and a Newton-Raphson root polisher: implementations targeting Xilinx Virtex and Virtex-ii fpgas can run up to 55 times faster than hardware pipelines developed using other methods, at the expense of a 50% increase in area. © 2004 IEEE.

关键词： Data flow analysis

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Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications

Compact and efficient encryption/decryption module for FPGA ...

引用

International conference on Information technology - Coding and computing

作者： Rouvroy, G Standaert, FX Quisquater, JJ Legat, JD Catholic Univ Louvain Microelect Lab UCL Crypto Grp B-1348 Louvaine La Neuve Belgium

ISBN: (纸本)0769521088

Hardware implementations of the Advanced Encryption Standard (AES) Rijndael algorithm have recently been the object of an intensive evaluation. Several papers describe efficient architectures for ASICs(1) and fpgas(2). In this context, the highest effort was devoted to high throughput (up to 20 Gbps) encryption-only designs, fewer works studied low area encryption-only architectures and only a few papers have investigated low area encryption/decryption structures. However in practice, only a few applications need throughput up to 20 Gbps while flexible and low cost encryption/decryption solutions are needed to protect sensible data, especially for embedded hardware applications. This paper proposes an efficient solution to combine Rijndael encryption and decryption in one FPGA design, with a strong focus on low area constraints. The proposed design fits into the smallest Xilinx fpgas(3), deals with data streams of 208 Mbps, uses 163 slices and 3 RAM blocks and improves by 68% the best-known similar designs in terms of ratio Throughput/Area. We also propose implementations in other FPGA Families (Xilinx Virtex-ii) and comparisons with similar DES, triple-DES and AES implementations.

关键词： cryptography AES DES FPGA compact encryption/decryption implementation

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Cryptarray A Scalable And reconfigurable Architecture For Cryptographic applications

Cryptarray A Scalable And Reconfigurable Architecture For Cr...

引用

作者： Michael John Lomonaco University of Central Florida

学位级别：硕士

Cryptography is increasingly viewed as a critical technology to fulfill the requirements of security and authentication for information exchange between Internet applications. However, software implementations of cryptographic applications are unable to support the quality of service from a bandwidth perspective required by most Internet applications. As a result, various hardware implementations, from Application-Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (fpgas), to programmable processors, were proposed to improve this inadequate quality of service. Although these implementations provide performances that are considered better than those produced by software implementations, they still fall short of addressing the bandwidth requirements of most cryptographic applications in the context of the Internet for two major reasons: (i) The majority of these architectures sacrifice flexibility for performance in order to reach the performance level needed for cryptographic applications. This lack of flexibility can be detrimental considering that cryptographic standards and algorithms are still evolving. (ii) These architectures do not consider the consequences of technology scaling in general, and particularly interconnect related problems. As a result, this thesis proposes an architecture that attempts to address the requirements of cryptographic applications by overcoming the obstacles described in (i) and (ii). To this end, we propose a new reconfigurable, two-dimensional, scalable architecture, called CRYPTARRAY, in which bus-based communication is replaced by distributed shared memory communication. At the physical level, the length of the wires will be kept to a minimum. CRYPTARRAY is organized as a chessboard in which the dark and light squares represent Processing Elements (PE) and memory blocks respectively. The granularity and resource composition of the PEs is specifically designed to support the computing operations encountered in cr

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Automating optimized table-with-polynomial function evaluation for fpgas

Automating optimized table-with-polynomial function evaluati...

引用

14th International conference on Field Programmable Logic and applications, FPL 2004

作者： Lee, Dong-U Mencer, Oskar Pearce, David J. Luk, Wayne Department of Computing Imperial College London United Kingdom

ISBN: (纸本)3540229892

Function evaluation is at the core of many compute-intensive applications which perform well on reconfigurable ***, in order to implement function evaluation efficiently, the FPGA programmer has to choose between a multitude of function evaluation methods such as table lookup, polynomial approximation, or table lookup combined with polynomial approximation. In this paper, we present a methodology and a partially automated implementation to select the best function evaluation hardware for a given function, accuracy requirement, technology mapping and optimization metrics, such as area, throughput and latency. The automation of function evaluation unit design is combined with ASC,A Stream Compiler, for fpgas. On the algorithmic side, MATLAB designs approximation algorithms with polynomial coefficients and minimizes bitwidths. On the hardware implementation side, ASC provides partially automated design space exploration. We illustrate our approach for sin(x), log(1+x) and 2x with a selection of graphs that characterize the design space with various dimensions, including accuracy, precision and function evaluation method. We also demonstrate design space exploration by implementing more than 400 distinct designs. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Field programmable gate arrays (FPGA)

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A high performance reconfigurable implementation of DES-like algorithms

A high performance reconfigurable implementation of DES-like...

引用

International conference on Microelectronics, ICM

作者： A. Valizadeh M. Saheb Zamani B. Sadeghian F. Mehdipour B. Najafi Department of Computer Engineering and IT Amirkabir University of Technology Tehran Tehran IRAN Department of Computer Engineering and IT Amirkabir University of Technology Tehran IRAN

reconfigurable computing has grown to become an important and large field of research. It offers advantages over traditional hardware and software implementation of computational algorithms. It is based on using field programmable gate arrays (fpgas), which can be configured after fabrication to take advantage of a hardware design but still maintain the flexibility of software. Particular applications, including encryption, which involve repetitive computation, and have inherent parallelism, are specifically well suited to the use of fpgas. In this paper, we implemented four DES-like algorithms namely DES, DESX, Biham-DES, and S/sup n/ DES on a reconfigurable hardware so that each algorithm could be replaced by another with low reconfiguration overhead time. This kind of implementation not only has high flexibility but also has an acceptable encryption rate compared with the fastest implementation of DES.

关键词： Hardware Public key cryptography Field programmable gate arrays Software algorithms Public key Fabrication Concurrent computing Parallel processing Data communication Application software

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reconfigurable supercomputing

Reconfigurable supercomputing

引用

IEEE/ACS International conference on Pervasive Services (ICPS)

作者： T. El-Ghazawi George Washington University USA

Summary form only given. The synergistic advances in high-performance computing and in reconfigurable computing, based on field programmable gate arrays (fpgas), form the basis for a new paradigm in supercomputing, namely reconfigurable supercomputing. This can be achieved through hybrid systems of microprocessors and FPGA modules that can leverage the system level concepts from high-performance computing and extend them to accommodate reconfigurations. Such systems inherently support both fine-grain and coarse-grain parallelism, and can dynamically tune their architecture to fit the applications. Many researchers have recognized this and advances are proceeding at three system levels. At the networked computing level, researchers have extended job management systems to recognize networked reconfigurable resources and exploit their power, in a grid computing fashion. Progress has been also made in programming and managing computer clusters, with reconfigurable co-processors. Finally, steps have been taken towards the development of massively parallel systems of conventional microprocessors and reconfigurable computing capabilities. Programming such systems can be quite challenging as programming FPGA devices can essentially involve hardware design. However, there have been very significant developments in compiler technologies and programming tools for some of these systems. This paper introduces the field of reconfigurable supercomputing and its advances in systems, programming, applications, and compiler technology.

关键词： Field programmable gate arrays Microprocessors Grid computing Power system management Program processors Parallel processing Computer architecture Application software Computer networks Computer network management

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Effective system and performance benchmarking for reconfigurable computers

Effective system and performance benchmarking for reconfigur...

引用

IEEE International conference on Field-Programmable technology (FPT)

作者： C. Esmail E.-G. Tarek G. Kris A. Nikitas P. Dan George Washington University USA George Mason University Hong Kong China SRC Computers Inc.

applications running on a reconfigurable computer can be divided into two major categories: computationally intensive and input/output intensive. In the first case, the input and output are limited, and therefore the performance of the reconfigurable computer depends primarily on the power of the fpgas, and the capability to exploit parallelism available in a given application. In the second case, the execution time is dominated by input/output, and therefore, an application cannot process data faster than the speed of its slowest input/output channel. The focus of This work is on developing micro-benchmarks to characterize the behavior of various communication channels within reconfigurable computers for the second class of applications. The paper defines a system of 'paper and pencil' micro-benchmarks for the measurement of maximum throughput and minimum latency in the communication between various components of a generic reconfigurable system. The results help to dynamically characterize a reconfigurable machine and the SRC 6E reconfigurable computer is used as a test case to validate the proposed model.

关键词： Field programmable gate arrays Random access memory Application software Delay reconfigurable architectures Microprocessors Benchmark testing Hardware design languages Concurrent computing Parallel processing

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Pipelining designs with loop-carried dependencies

Pipelining designs with loop-carried dependencies

引用

IEEE International conference on Field-Programmable technology (FPT)

作者： H. Styles D.B. Thomas W. Luk Department of Computing Imperial College London London UK

This work explores the reconfigurable dataflow approach in producing efficient hardware pipelines for programs with loop-carry dependencies in nested loops. reconfigurable dataflow combines static and dynamic scheduling, and employs tagged tokens to enable reassembling of results which can retire out of order. The effectiveness of this approach is illustrated using a fractal set generator and a Newton-Raphson root polisher: implementations targeting Xilinx Virtex and Virtex-ii fpgas can run up to 55 times faster than hardware pipelines developed using other methods, at the expense of a 50% increase in area.

关键词： Pipeline processing Hardware Concurrent computing Dynamic scheduling Fractals Distributed control Educational institutions Field programmable gate arrays Optimizing compilers Runtime

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