检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

408 篇 会议
9 篇 期刊文献
1 篇 学位论文

馆藏范围

418 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

221 篇 工学
- 210 篇 计算机科学与技术...
- 100 篇 软件工程
- 49 篇 电气工程
- 49 篇 电子科学与技术（可...
- 22 篇 控制科学与工程
- 17 篇 信息与通信工程
- 12 篇 动力工程及工程热...
- 7 篇 土木工程
- 5 篇 光学工程
- 5 篇 建筑学
- 5 篇 航空宇航科学与技...
- 5 篇 生物工程
- 4 篇 机械工程
- 4 篇 环境科学与工程（可...
- 3 篇 仪器科学与技术
- 2 篇 生物医学工程（可授...
66 篇 理学
- 39 篇 数学
- 17 篇 物理学
- 6 篇 生物学
- 6 篇 系统科学
- 4 篇 统计学（可授理学、...
- 2 篇 化学
- 1 篇 地球物理学
- 1 篇 地质学
13 篇 管理学
- 13 篇 管理科学与工程(可...
- 9 篇 工商管理
3 篇 经济学
- 3 篇 应用经济学
3 篇 医学
- 3 篇 临床医学
2 篇 教育学
- 2 篇 教育学
1 篇 法学
- 1 篇 社会学

主题

149 篇 field programmab...
96 篇 hardware
69 篇 computer archite...
35 篇 field programmab...
32 篇 application soft...
32 篇 fpga
24 篇 reconfigurable a...
20 篇 runtime
20 篇 acceleration
19 篇 parallel process...
19 篇 reconfigurable c...
16 篇 routing
16 篇 digital signal p...
15 篇 high performance...
14 篇 concurrent compu...
14 篇 reconfigurable l...
14 篇 random access me...
14 篇 clocks
12 篇 bandwidth
12 篇 microprocessors

机构

7 篇 department of co...
5 篇 george washingto...
4 篇 institute for re...
3 篇 rochester instit...
3 篇 george mason uni...
3 篇 karlsruhe instit...
3 篇 xilinx inc san j...
2 篇 heinz nixdorf in...
2 篇 chengdu universi...
2 篇 northeastern uni...
2 篇 brocade communic...
2 篇 department of el...
2 篇 institute of com...
2 篇 embedded softwar...
2 篇 department of el...
2 篇 variel microelec...
2 篇 institut für tec...
2 篇 institute for se...
2 篇 faculty of elect...
2 篇 department of el...

作者

9 篇 luk wayne
6 篇 wayne luk
4 篇 cheung peter y. ...
4 篇 axel jantsch
4 篇 zhonghai lu
4 篇 t. el-ghazawi
4 篇 ming liu
4 篇 peter y. k. cheu...
4 篇 wolfgang kuehn
3 篇 s.j. visser
3 篇 david kearney
3 篇 sonia lopez
3 篇 a.s. dawood
3 篇 j.a. williams
3 篇 john wawrzynek
3 篇 e. el-araby
3 篇 sven-ole voigt
3 篇 shaoyi cheng
3 篇 w. luk
3 篇 prasanna viktor ...

语言

411 篇 英文
7 篇 其他

检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

共 418 条记录，以下是351-360 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications

Compact and efficient encryption/decryption module for FPGA ...

引用

International conference on Information technology: Coding and computing (ITCC)

作者： G. Rouvroy F.-X. Standaert J.-J. Quisquater J.-D. Legat Laboratoire de Micro electronique Universite Catholique de Louvain Louvain-la-Neuve Belgium

Hardware implementations of the advanced encryption standard (AES) Rijndael algorithm have recently been the object of an intensive evaluation. Several papers describe efficient architectures for ASICs and fpgas. In this context, the highest effort was devoted to high throughput (up to 20 Gbps) encryption-only designs, fewer works studied low area encryption-only architectures and only a few papers have investigated low area encryption/decryption structures. However, in practice, only a few applications need throughput up to 20 Gbps while flexible and low cost encryption/decryption solutions are needed to protect sensible data, especially for embedded hardware applications. We purpose an efficient solution to combine Rijndael encryption and decryption in one FPGA design, with a strong focus on low area constraints. The proposed design fits into the smallest Xilinx fpgas, deals with data streams of 208 Mbps, uses 163 slices and 3 RAM blocks and improves by 68% the best-known similar designs in terms of ratio Throughput/Area. We also propose implementations in other FPGA Families (Xilinx Virtex-ii) and comparisons with similar DES, triple-DES and AES implementations.

关键词： Cryptography Field programmable gate arrays Throughput Hardware Costs NIST Computer architecture Iterative algorithms Protection Application specific integrated circuits

来源：评论

学校读者我要写书评

暂无评论

Implementation of Cellular Learning Automata on reconfigurable computing Systems

Implementation of Cellular Learning Automata on Reconfigurab...

引用

CCECE 2003 Canadian conference on Electrical and Computer Engineering: Toward a Caring and Humane technology

作者： Zamani, Morteza Saheb Mehdipour, Farhad Meybodi, Mohammad Reza Computer Engineering Department Amirkabir University of Technology Tehran Iran

reconfigurable computing systems (RCS) use the flexibility of programmable devices and the speed of hardware to implement high performance systems. Implementation of RCS is normally made by means of programmable devices, such as fpgas. On the other hand, recently, cellular learning automata (CLA) have been proposed as a combination of conventional cellular automaton and learning automaton. Software simulation of CLA has shown it to be successful for solving some hard problems. However, the process on conventional computers is slow. To overcome this problem, we implemented CLA in hardware. In addition, for some applications which necessitate run time changes for parameters, the ability of run-time reconfiguration (RTR) in hardware is a solution. In this paper, the design and implementation of CLA on a reconfigurable system are presented. Experimental results show considerable speedup gain of RCS version over the software version. Independence on CLA dimensions is another benefit of reconfigurable hardware implementation of CLA. In other words, by increasing the dimensions of CLA, the time needed for running reconfigurable CLA implemented, on hardware remains constant.

关键词： Computer software

来源：评论

学校读者我要写书评

暂无评论

Exploiting Fine-Grain Parallelism of IDEA Using Xilinx FPGA 16

Exploiting Fine-Grain Parallelism of IDEA Using Xilinx FPGA

引用

16th International conference on Parallel and Distributed computing Systems, PDCS 2003

作者： Pan, Zexin Venkateswaran, Srikanth Gurumani, Swathi Tanjore Wells, B. Earl Department of Electrical and Computer Engineering University of Alabama in Huntsville HuntsvilleAL35899 United States

ISBN: (纸本)9781618398161

A high performance implementation of the International Data Encryption Algorithm (IDEA) that targets the Xilinx Vertex-ii XC2V1000-6 FPGA is presented in this paper. fpgas have proven to be very efficient in implementing encryption algorithms. The high throughput of this implementation is achieved by means of exploiting both fine-grain and coarse-grain parallelism present in the IDEA operations as wells as by taking advantage of embedded multipliers that are present in Xilinx FPGA. Our fully pipelined single-chip implementation offers a 6 Gbits/sec throughput at a 95 MHz system clock rate, which is better than any of the existing single-chip implementations. This design could be of great use in many real-time applications. © PDCS 2003. All rights reserved.

关键词： reconfigurable architectures

来源：评论

学校读者我要写书评

暂无评论

A Preliminary Study of Molecular Dynamics on reconfigurable Computers

A Preliminary Study of Molecular Dynamics on Reconfigurable ...

引用

Proceedings of the International conference on Engineering of reconfigurable Systems and Algorithms, ERSA'03

作者： Wolinski, Christophe Trouw, Frans Gokhale, Maya Los Alamos National Laboratory Los Alamos NM United States IRISA IFSIC France

ISBN: (纸本)193241505X

In this paper we investigate the performance of platform fpgas on a compute-intensive, floating-point-intensive supercomputing application, Molecular Dynamics (MD). MD is a popular simulation technique to track interacting particles through time by integrating their equations of motion. One part of the MD algorithm was implemented using the Fabric Generator (FG)[10] and mapped onto several reconfigurable logic arrays. FG is a Java-based toolset that greatly accelerates construction of the fabrics from an abstract technology independent representation. Our experiments used technology-independent IEEE 32-bit floating point operators[2] so that the design could be easily re-targeted. Experiments were performed using both non-pipelined and pipelined floating point modules. We present results for the Altera Excalibur ARM System on a Programmable Chip (SoPC), the Altera Stratix EP1S80, and the Xilinx Virtex-ii Pro 2VP50. The best results obtained were 5.69 GFlops at 80MHz (Altera Stratix EP1S80), and 4.47 GFlops at 82 MHz (Xilinx Virtex-ii Pro 2VP50). Assuming a 10W power budget, these results compare very favorably to a 4Gflop/60W processing/power rate for a modern Pentium, suggesting that reconfigurable logic can achieve high performance at low power on floating-point-intensive applications.

关键词： Molecular dynamics

来源：评论

学校读者我要写书评

暂无评论

Hardware implementations of real-time reconfigurable WSAT variants

Hardware implementations of real-time reconfigurable WSAT va...

引用

13th International conference on Field-Programmable Logic and applications, FPL 2003

作者： Yap, Roland H. C. Wang, Stella Z. Q. Henz, Martin J. School of Computing National University of Singapore Singapore

ISBN: (纸本)3540408223

Local search methods such as WSAT have proven to be successful for solving SAT problems. In this paper, we propose two host-FPGA (Field Programmable Gate Array) co-implementations, which use modified WSAT algorithms to solve SAT problems. Our implementations are reconfigurable in real-time for different problem instances. On an XCV1000 FPGA chip, SAT problems up to 100 variables and 220 clauses can be solved. The first implementation is based on a random strategy and achieves one flip per clock cycle through the use of pipelining. The second uses a greedy heuristic at the expense of FPGA space consumption, which precludes pipelining. Both of the two implementations avoid re-synthesis, placement, routing for different SAT problems, and show improved performance over previously published reconfigurable SAT implementations on fpgas. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Abstractions and primitives enabling runtime resource allocation for dynamic IP cores using virtual platform fpgas

Abstractions and primitives enabling runtime resource alloca...

引用

IEEE International conference on Field-Programmable technology (FPT)

作者： D.A. Kearney G. Veldman D. Warren Adv. Comput. Res. Centre South Australia Univ. Mawson Lakes SA Australia Reconfigurable Computing Laboratory (RCL) University of South Australia Mawson Lakes SA Australia

The platform approach to hardware design was originally suggested as a method of broadening the domain of applications a custom VLSI chip can be applied to by introducing additional programmability. In this paper we extend the idea of platform design with the objective broadening the range of applications of fpgas by making runtime resource allocation available for fpgas that do not support run time reconfiguration natively. We explore this approach by constructing a virtual platform FPGA; that is a reconfigurable platform implemented on top of a native FPGA. The paper gives an overview of the application programmer's interface of our proposed virtual platform and some of the communication primitives that we have implemented to construct the virtual platform. We note that there is a need for more work in identifying computation primitives for a virtual platform that strike a balance between supporting useful abstractions and having efficient implementations on typical native fpgas.

关键词： Runtime Resource management Field programmable gate arrays Application software Hardware Productivity Costs Laboratories Australia Lakes

来源：评论

学校读者我要写书评

暂无评论

Combined run-time area allocation and long line re-routing for reconfigurable computing

Combined run-time area allocation and long line re-routing f...

引用

IEEE International conference on Field-Programmable technology (FPT)

作者： M.D. Jasiunas Reconfigurable Computing Laboratory Advanced Computing Research Centre University of South Australia Mawson Lakes SA Australia

On-line (run time) algorithms for allocation of area and routing resources are a requirement if field programmable logic applications are to be loaded to the FPGA at the arbitrary request of users. Long lines are the preferred interconnect for such applications on dense fpgas as they provide low delay channels. In this paper we investigate the combination of an area allocation algorithm based on the Minkowski sum with run time routing based on line probing for applications that are linked only by long lines. We show by construction that allocation and routing are feasible at run time using these algorithms. The paper then introduces a new metric to measure the performance of dynamic run time resource allocation on fpgas. The new metric measures fragmentation of resources in an environment where applications selected from statistical distributions of area and execution time are continuously queued for placement on the FPGA. It is argued that this metric is more realistic compared to other measures which are based on static model of allocation. A simulation of this dynamic FPGA environment has revealed new behaviours related to run time reconfiguration. Firstly, to maintain full utilisation of the area resources of the FPGA, it will be necessary to queue tasks prior to execution. The queuing time of these tasks is an added overhead not previously reported. Secondly, small area applications may block other applications due to the exhaustion of long line routing resources. This adds to the other already observed blocking behaviour where large area cores may so dominate the FPGA area that further allocation is prevented. A new operation for the aggregation of small cores is proposed in this paper to overcome blocking associated with routing.

关键词： Runtime Field programmable gate arrays Routing Resource management Time measurement reconfigurable logic Programmable logic arrays Programmable logic devices Delay Area measurement

来源：评论

学校读者我要写书评

暂无评论

Implementation of cellular learning automata on reconfigurable computing systems

Implementation of cellular learning automata on reconfigurab...

引用

Canadian conference on Electrical and Computer Engineering (CCECE)

作者： M.S. Zamani F. Mehdipour M.R. Meybodi Computer Engineering Department Amirkabir University of Technology슠 Iran

关键词： Learning automata Hardware Lattices Content addressable storage Stochastic processes Inverse problems Field programmable gate arrays Computational modeling Application software Runtime

来源：评论

学校读者我要写书评

暂无评论

Exploiting system-level parallelism in the application development on a reconfigurable computer

Exploiting system-level parallelism in the application devel...

引用

IEEE International conference on Field-Programmable technology (FPT)

作者： E. El-Araby M. Taher K. Gaj T. El-Ghazawi D. Caliga N. Alexandridis George Washington University USA George Mason University USA SRC Computers Inc.

reconfigurable Computers (RCs) can leverage the synergism between conventional processors and fpgas to provide low-level hardware functionality at the same level of programmability as general-purpose computers. In a large class of applications, the total I/O time is comparable or even greater than the computations time. As a result, the rate of the DMA transfer between the microprocessor memory and the on-board memory becomes the performance bottleneck even on RCs. In this paper, we perform a theoretical and experimental study of this specific performance limitation for the state-of-the art reconfigurable platform, SRC-6E. We demonstrate and quantify the possible solution to this problem that exploits the system-level parallelism within the reconfigurable machine.

关键词： Parallel processing Application software Concurrent computing Microprocessors Hardware Tiles Field programmable gate arrays Computer architecture Computer hacking Logic programming

来源：评论

学校读者我要写书评

暂无评论

Use of hardware and software information processing in mechatronics on the example of an adaptive control

Use of hardware and software information processing in mecha...

引用

IEEE International conference on Industrial technology (ICIT)

作者： T. Reinemann R. Kasper Insitute of Mechatronics and Drive Technology Otto-von-Guericke University of Magdeburg Magdeburg Germany

Today micro-controllers and signal processors are the standard-implementing platform for embedded controllers. But often their performance cannot keep pace with requirements for demanding applications, for example in mechatronic systems. Usually, in this case the microcontroller is replaced by a faster one. But this doesn't avoid software problems arising in realtime applications even by using high-level languages and always by using assembler language. Further problems are concerned with higher clock frequencies and energy consumption. On the other hand fpgas are very well suited for high-speed applications, because information processing can be performed in parallel. But they usually lack common mathematical function libraries, so that control and filter algorithms have to be implemented in a time consuming and expensive process. Today's fpgas offer a huge number of gates, so that even a processor core can be implemented inside. This enables a combination of hardware and software signal processing within only one IC. Thereby the available software can be used further on and only some algorithms requiring high performance have to be implemented in hardware. Furthermore some aspects of reconfigurable computing are treated.

关键词： Hardware Information processing Mechatronics Adaptive control Application software Signal processing algorithms Field programmable gate arrays Software performance Signal processing Microcontrollers

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共42页 << < 32 33 34 35 36 37 38 39 40 41 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：