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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

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A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory 03

A reconfigurable signal processing IC with embedded FPGA and...

引用

Proceedings of the 40th annual Design Automation conference

作者： M. Borgatti L. Calì G. De Sandre B. Forêt D. Iezzi F. Lertora G. Muzzi M. Pasotti M. Poles P. L. Rolandi STMicroelectronics Central R&D Agrate Brianza Italy

ISBN: (纸本)9781581136883

A 1GOPS dynamically reconfigurable processing unit with embedded Flash memory and SRAM-based FPGA targets image-voice processing and recognition applications. Code, data and FPGA bitstreams are stored in the embedded Flash memory and are independently accessible through 3 content-specific, 64-bit I/O ports with a peak read rate of 1.2GB/s. The system is implemented in a 0.18um, 2PL-6ML CMOS Flash technology, chip area is 70mm2.

关键词： multimedia computing reconfigurable architectures application-specific integrated circuits (ASICs) field-programmable gate arrays (fpgas) digital signal processors integrated circuit design

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Evaluation of network topologies for a run time re-routable network on a programmable chip

Evaluation of network topologies for a run time re-routable ...

引用

IEEE International conference on Field-Programmable technology (FPT)

作者： D.A. Kearney G. Veldman Reconfigurable Computing Laboratory University of South Australia Reconfigurable Computing Laboratory University of South Australia Australia

Networks on a chip have become a popular way to integrate IP cores. In the field programmable logic domain there is the added possibility that IP cores can be added and removed from the chip using run time reconfiguration. The widely advocated fixed mesh packet forwarding network topology, where the cores are placed in fixed sized tiles created by the mesh, may lead to area fragmentation when the cores and the tiles are not exactly the same size. An alternative is to allow variable sized cores to be placed in any free location and to re-route the network to connect to them. We report here on a study that re-evaluates the classic network topologies against criteria that reflect an FPGA environment were the network might be rerouted as each new core is placed or removed from the FPGA. The most promising network configuration, a set of star connected tristate busses with token ring arbitration, (which we call a RingBuss) has been implemented. Its performance and area overheads are compatible with applications suitable for one million gate equivalent fpgas.

关键词： Network topology Programmable logic arrays Programmable logic devices Network-on-a-chip Field programmable gate arrays Tiles Computer networks Routing Prototypes Computer network management

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Single instruction set Architectures for image processing

Single instruction set Architectures for image processing

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conference on reconfigurable technology - fpgas and reconfigurable Processors for computing and Communications IV

作者： Laplante, P Gilreath, W Penn State Great Valley Malvern PA 19355 USA

ISBN: (纸本)0819446467

For more than fifty years, computer engineers have sought to construct minimal computers using only a single instruction computer. While it might appear to be a simple academic exercise, remarkably, a rich computation paradigm can be developed using this approach, with important applications and implications in reconfigurable, chemical, optical and biological computing. More recently, the widespread use of the Field Programmable Gate Array (FPGA) has made such an approach not only desirable, but also practical. In this paper the history and motivation behind single instruction or one instruction computing (OISC) is reviewed. It is then shown how the paradigm can be used to implement a variety of imaging operations efficiently. Finally, a practical application and future work in languages and tools are presented.

关键词： OISC one-instruction computing image processing reconfigurable computing

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On-board satellite image compression using reconfigurable fpgas 1

On-board satellite image compression using reconfigurable FP...

引用

IEEE International conference on Field-Programmable technology (FPT)

作者： Dawood, AS Williams, JA Visser, SJ Queensland Univ Technol Cooperat Res Ctr Satellite Syst Brisbane Qld 4001 Australia

ISBN: (纸本)0780375742

Remote sensing satellites operate almost exclusively a store-and-forward mode, with acquired imagery stored on board until being downlinked when ground stations come within view. Space-borne imaging sensors generate tremendous volumes of data at very high rates, however storage capacity and communication bandwidth are expensive satellite resources. By compressing the images as they are acquired, better use is made of available storage and bandwidth capacity. reconfigurable computing technology, which combines the flexibility of traditional microprocessors with the performance of ASIC devices, is very promising for space applications. The High Performance computing (HPC-I) payload, based on a radiation hardened reconfigurable FPGA has been developed and integrated into the Australian scientific mission satellite FedSat. HPC-I is a testbed in space to validate reconfigurable logic for a variety of satellite applications. The design and implementation on HPC-I of the On-Board Image Compression System (OBICS) is presented, and its compression performance evaluated using JPEG standard as a benchmark. The results indicate that fpgas and HPC-I are suitable platforms for such systems, and that satisfactory compression can only be achieved with moderately complex logic designs.

关键词： Image compression

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Framework for development and distribution of hardware acceleration

Framework for development and distribution of hardware accel...

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conference on reconfigurable technology - fpgas and reconfigurable Processors for computing and Communications IV

作者： Thomas, DB Luk, W Univ London Imperial Coll Sci Technol & Med Dept Comp London SW7 2BZ England

ISBN: (纸本)0819446467

This paper describes IGOL, a framework for developing reconfigurable data processing applications. While IGOL was originally designed to target imaging and graphics systems, its structure is sufficiently general to support a broad range of applications. IGOL adopts a four-layer architecture: application layer, operation layer, appliance layer and configuration layer. This architecture is intended to separate and co-ordinate both the development and execution of hardware and software components. Hardware developers can use IGOL as an instance testbed for verification and benchmarking, as well as for distribution. Software application developers can use IGOL to discover hardware accelerated data processors, and to access them in a transparent, non-hardware specific manner. IGOL provides extensive support for the RC1000-PP board via the Handel-C language, and a wide selection of image processing filters have been developed. IGOL also supplies plug-ins to enable such filters to be incorporated in popular applications such as Premiere, Winamp, VirtualDub and DirectShow. Moreover, IGOL allows the automatic use of multiple cards to accelerate an application, demonstrated using DirectShow. To enable transparent acceleration without sacrificing performance, a three-tiered COM (Component Object Model) API has been designed and implemented. This API provides a well-defined and extensible interface which facilitates the development of hardware data processors that can accelerate multiple applications.

关键词： reconfigurable hardware FPGA hardware acceleration component object model

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Minimizing energy dissipation of matrix multi-plication kernel on Virtex-ii

Minimizing energy dissipation of matrix multi-plication kern...

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conference on reconfigurable technology - fpgas and reconfigurable Processors for computing and Communications IV

作者： Choi, S Prasanna, VK Jang, JW Univ So Calif Los Angeles CA 90089 USA

ISBN: (纸本)0819446467

In this paper, we develop energy-efficient designs for matrix multiplication on fpgas. To analyze the energy dissipation, we develop a high-level model using domain-specific modeling techniques. In this model, we identify architecture parameters that significantly affect the total energy (system-wide energy) dissipation. Then, we explore design trade-offs by varying these parameters to minimize the system-wide energy. For matrix multiplication, we consider a uniprocessor architecture and a linear array architecture to develop energy-efficient designs. For the uniprocessor architecture, the cache size is a parameter that affects the I/O complexity and the system-wide energy. For the linear array architecture, the amount of storage per processing element is a parameter affecting the system-wide energy. By using maximum amount of storage per processing element and minimum number of multipliers, we obtain a design that minimizes the system-wide energy. We develop several energy-efficient designs for matrix multiplication. For example, for 6 x 6 matrix multiplication, energy savings of upto 52% for the uniprocessor architecture and 36% for the linear arrary architecture is achieved over an optimized library for Virtex-ii FPGA from Xilinx.

关键词： matrix multiplication domain specific modeling energy efficient design fpgas

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reconfigurable fpgas for real time image processing in space 14

Reconfigurable FPGAS for real time image processing in space

引用

14th International conference on Digital Signal Processing, DSP 2002

作者： Dawood, Anwar S. Visiter, Stephen J. Williams, John A. Cooperative Research Centre for Satellite Systems Queensland University of Technology BrisbaneQLD4001 Australia

ISBN: (纸本)0780375033

Programmable logic offers an efficient solution for the performance and flexibility required by real time image processing systems. Application Specific Integrated Circuit (ASIC) devices could provide such performance, but the lack of flexibility for changing operation requirements and the associated high development and production cost limit their acceptance for space applications. Field Programmable Gate Arrays (fpgas) offer highly flexible designs, scalable circuits, and real time system performance. The parallel processing power of fpgas allows data to be processed more quickly than a similar microprocessor implementation. The High Performance computing (HPC-I) payload for the Australian scientific mission satellite FedSat has been designed and manufactured to validate the use of FPGA technology onboard satellites for a variety of space applications. This paper elaborates on implementing image processing algorithms and techniques on fpgas for space applications. It presents the implementation, testing and performance evaluation of a Gaussian filter and Convolution Engine on HPC-I. © 2002 IEEE.

关键词： Space applications

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FPGA based real-time adaptive filtering for space applications 1

FPGA based real-time adaptive filtering for space applicatio...

引用

IEEE International conference on Field-Programmable technology (FPT)

作者： Visser, SJ Dawood, AS Williams, JA Queensland Univ Technol Cooperat Res Ctr Satellite Syst Brisbane Qld 4001 Australia

ISBN: (纸本)0780375742

Satellites and other space-based signal processing systems face a challenging operating environment. In addition to radiation related effects, the satellites themselves are often electrically noisy, resulting in high levels of noise and interference in data signals. Digital signal processing systems such as adaptive filters are vital components for the next generation of satellites. Most current satellite systems have limited computing resources for on-board digital signal processing and lack flexibility to adapt to changing operation requirements. The deployment of reconfigurable Field Programmable Gate Array (FPGA) technology on-board satellites is a very promising solution for digital signal processing in space, as they offer flexibility, scalability and high performance. The High Performance computing (HPC-I) payload integrated into the Australian scientific mission satellite FedSat is designed to evaluate the deployment of FPGA technology for a variety of space applications. This paper elaborates on implementing rule-based adaptive filtering techniques on fpgas for space applications, presenting the design and implementation of an adaptive Finite Impulse Response (FIR) filter on HPC-I. A fuzzy adaptive image filtering algorithm for remote sensing applications is also considered.

关键词： Adaptive filtering

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On-board satellite image compression using reconfigurable fpgas

On-board satellite image compression using reconfigurable FP...

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IEEE International conference on Field-Programmable technology (FPT)

作者： A.S. Dawood J.A. Williams S.J. Visser The Cooperative Research Centre for Satellite System Queensland University of Technology Brisbane QLD Australia

Remote sensing satellites operate almost exclusively in a store-and-forward mode, with acquired imagery stored on board until being downlinked when ground stations come within view. Space-borne imaging sensors generate tremendous volumes of data at very high rates, however storage capacity and communication bandwidth are expensive satellite resources. By compressing the images as they are acquired, better use is made of available storage and bandwidth capacity. reconfigurable computing technology, which combines the flexibility of traditional microprocessors with the performance of ASIC devices, is very promising for space applications. The High Performance computing (HPC-I) payload, based on a radiation hardened reconfigurable FPGA has been developed and integrated into the Australian scientific mission satellite FedSat. HPC-I is a testbed in space to validate reconfigurable logic for a variety of satellite applications. The design and implementation on HPC-I of the On-Board Image Compression System (OBICS) is presented, and its compression performance evaluated using JPEG standard as a benchmark. The results indicate that fpgas and HPC-I are suitable platforms for such systems, and that satisfactory compression can only be achieved with moderately complex logic designs.

关键词： Image coding Field programmable gate arrays Image storage Bandwidth Space technology Remote sensing Satellite ground stations Capacitive sensors Image sensors Artificial satellites

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reconfigurable fpgas for real time image processing in space

Reconfigurable FPGAS for real time image processing in space

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International conference on Digital Signal Processing (DSP)

作者： A.S. Dawood S.J. Visser J.A. Williams The Cooperative Research Centre for Satellite Systems Queensland University of Technology Brisbane QLD Australia

Programmable logic offers an efficient solution for the performance and flexibility required by real time image processing systems. Application specific integrated circuit (ASIC) devices could provide such performance, but the lack of flexibility for changing operation requirements and the associated high development and production cost limit their acceptance for space applications. Field programmable gate arrays (fpgas) offer highly flexible designs, scalable circuits, and real time system performance. The parallel processing power of fpgas allows data to be processed more quickly than a similar microprocessor implementation. The High Performance computing (HPC-I) payload for the Australian scientific mission satellite FedSat has been designed and manufactured to validate the use of FPGA technology onboard satellites for a variety of space applications. This paper elaborates on implementing image processing algorithms and techniques on fpgas for space applications. It presents the implementation, testing and performance evaluation of a Gaussian filter and convolution engine on HPC-I.

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