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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

共 418 条记录，以下是371-380 订阅

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FPGA based real-time adaptive filtering for space applications

FPGA based real-time adaptive filtering for space applicatio...

引用

IEEE International conference on Field-Programmable technology (FPT)

作者： S.J. Visser A.S. Dawood J.A. Williams The Cooperative Research Centre for Satellite System Queensland University of Technology Brisbane QLD Australia

Satellites and other space-based signal processing systems face a challenging operating environment. In addition to radiation related effects, the satellites themselves are often electrically noisy, resulting in high levels of noise and interference in data signals. Digital signal processing systems such as adaptive filters are vital components for the next generation of satellites. Most current satellite systems have limited computing resources for on-board digital signal processing and lack flexibility to adapt to changing operation requirements. The deployment of reconfigurable field programmable gate array (FPGA) technology on-board satellites is a very promising solution for digital signal processing in space, as they offer flexibility, scalability and high performance. The high performance computing (HPC-I) payload integrated into the Australian scientific mission satellite FedSat is designed to evaluate the deployment of FPGA technology for a variety of space applications. This paper elaborates on implementing rule-based adaptive filtering techniques on fpgas for space applications, presenting the design and implementation of an adaptive finite impulse response (FIR) filter on HPC-I. A fuzzy adaptive image filtering algorithm for remote sensing applications is also considered.

关键词： Field programmable gate arrays Adaptive filters Satellites Space technology Digital signal processing Working environment noise Noise level Finite impulse response filter Adaptive signal processing Face

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reconfigurable processors for handhelds and wearables:: Application analysis

Reconfigurable processors for handhelds and wearables:: Appl...

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conference on reconfigurable technology - fpgas and reconfigurable Processors for computing and Communications iiI

作者： Enzler, R Platzner, M Plessl, C Thiele, L Tröster, G Swiss Fed Inst Technol Swiss Fed Inst Technol CH-8092 Zurich Switzerland

ISBN: (纸本)0819442496

In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core.

关键词： benchmarking handhelds wearables processor simulator dynamically reconfigurable processor

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A run-time reconfigurable 2D discrete wavelet transform using JBits

A run-time reconfigurable 2D discrete wavelet transform usin...

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conference on reconfigurable technology - fpgas and reconfigurable Processors for computing and Communications iiI

作者： Ballagh, J Athanas, P Keller, E Virginia Tech Blacksburg VA 24061 USA

ISBN: (纸本)0819442496

With the growth in high performance multimedia applications, specialized hardware for certain tasks is desirable. While ASICs provide a solution addressing performance, they are unable to provide an optimal solution for a given problem instance. fpgas can be used with run-time reconfiguration to dynamically customize a circuit. Optimizations leading to faster circuits and reduced logic can result. The paper discusses the implementation of a run-time parameterizable 2D Discrete Wavelet Transform core using the JBits tool suite. The motivation for such a core is discussed. as well the benefits afforded by dynamic circuit specialization.

关键词： wavelets DWT compression RTR JBits FPGA

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Model-based performance analysis for reconfigurable coprocessors

Model-based performance analysis for reconfigurable coproces...

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conference on reconfigurable technology - fpgas and reconfigurable Processors for computing and Communications iiI

作者： Charlwood, SM Mangnall, JP Quigley, SF Univ Birmingham Digital Syst & Vis Proc Grp Birmingham W Midlands England

ISBN: (纸本)0819442496

Uni-processor and shared memory UMA multi-processor workstations are currently ubiquitous. The capabilities of such machines are commonly extended through the use of one or more application-specific coprocessors, located on the system expansion/peripheral bus, or a dedicated local bus. It is therefore considered worthwhile to investigate the limits of applicability of FPGA-based reconfigurable coprocessors when used to enhance such machines. In order to do this, it must be possible to estimate performance for coprocessor architectures that do not currently exist. This paper describes a method for generating estimates of performance for applications which make use of such reconfigurable coprocessors. By combining direct measurements on the target platform with model-based estimates and simulation data, estimates of performance can be synthesised which are accurate to better than +/-5%.

关键词： model-based performance analysis software acceleration reconfigurable coprocessors

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Programming high performance reconfigurable computers

Programming high performance reconfigurable computers

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conference on reconfigurable technology - fpgas and reconfigurable Processors for computing and Communications iiI

作者： Smith, MC Peterson, GD Univ Tennessee Dept Elect & Comp Engn Knoxville TN 37996 USA

ISBN: (纸本)0819442496

High Performance Computers (HPC) provide dramatically improved capabilities for a number of defense and commercial applications, but often are too expensive to acquire and to program. The smaller market and customized nature of HPC architectures combine to increase the cost of most such platforms. To address the problems with high hardware costs. one may create more inexpensive Beowolf clusters of dedicated commodity processors. Despite the benefit of reduced hardware costs. programming the HPC platforms to achieve high performance often proves extremely time-consuming and expensive in practice. In recent years. programming productivity gains come from the development of common APIs and libraries of functions to support distributed applications. Examples include PVM, MPI, BLAS, and VSIPL. The implementation of each API or library is optimized for a given platform. but application developers can write code that is portable across specific HPC architectures. The application of reconfigurable computing (RC) into HPC platforms promises significantly enhanced performance and flexibility at a modest cost. Unfortunately. configuring (programming) the reconfigurable computing nodes remains a challenging task and relatively little work to date has focused on potential high performance reconfigurable computing (HPRC) platforms consisting of reconfigurable nodes paired with processing nodes. This paper addresses the challenge of effectively exploiting HPRC resources by first considering the performance evaluation and optimization problem before turning to improving the programming infrastructure used for porting applications to HPRC platforms.

关键词： high performance computing reconfigurable computing programming performance evaluation

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XHWIF: A portable hardware interface for reconfigurable computing

XHWIF: A portable hardware interface for reconfigurable comp...

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conference on reconfigurable technology - fpgas and reconfigurable Processors for computing and Communications iiI

作者： Sundararajan, P Guccione, SA Levi, D Xilinx Inc San Jose CA 95124 USA

ISBN: (纸本)0819442496

As the interest in FPGA-based hardware has grown, so has the number and type of commercially available platforms. The greatest drawback to this proliferation of hardware platforms is the lack of standards. Even boards using identical hosts, FPGA devices and bus interfaces typically have widely varying software interfaces, limiting the portability of tools and applications across these platforms. Xilinx's XHWIF(tm) portable hardware interface attempts to address this problem. The XHWIF interface provides a software layer providing all necessary communication and control for generic FPGA-based hardware. This interface permits tools and applications to be run on a variety of platforms, typically without modifications or re-compilation. In addition, a remote network interface is supplied as part of XHWIF API. applications and tools which use the XHWIF interface can also run transparently across a network without modification. This permits not only sharing of hardware resources in a networked environment, but a simple way of implementing systems which use Remote Network Reconfiguration. XHWIF API is currently provided as part of Xilinx's JBits(tm) Software Development Kit.

关键词： FPGA reconfigurable computing hardware interface

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Temporal partitioning of circuits for advanced partially reconfigurable systems

Temporal partitioning of circuits for advanced partially rec...

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conference on reconfigurable technology - fpgas and reconfigurable Processors for computing and Communications iiI

作者： Mohan, R Dasu, A Panchanathan, S Arizona State Univ Dept Comp Sci & Engn Collaborat Program Ubiquitous Comp CUbiC Tempe AZ 85287 USA

ISBN: (纸本)0819442496

reconfigurable architectures are proving to be very effective in applications that involve the implementation of multiple compute-intensive algorithms, which share the same computing modules. With the advent of dynamically reconfigurable architectures, many temporal partitioning algorithms (TPA) have been proposed address the issue of area and time constraints. The main objective of TPA is to divide a large design into smaller sub-components so that they can be implemented over multiple reconfigurations. In this paper, we propose a new temporal partitioning process (TPP), which includes a modified TPA along with a port reallocation algorithm (PRA) to reduce the reconfiguration time to facilitate real-time implementation. The reduction in reconfiguration time is achieved by employing the knowledge of the function implemented in each logic block thereby effectively reusing the cells in the array in a selective manner. This avoids the need for complete reconfiguration and reduces the net reconfiguration time. The proposed approach has been tested on random graphs and on the MCNC benchmark circuits. Significant reduction in reconfiguration time has been achieved.

关键词： Logic Computer architecture Field programmable gate arrays Algorithm development Software Composites Computer engineering Computer science computing systems Multimedia

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Delivering Acceleration: The Potential for Increased HPC Application Performance Using reconfigurable Logic 01

Delivering Acceleration: The Potential for Increased HPC App...

引用

2001 ACM/IEEE conference on Supercomputing, SC 2001

作者： Caliga, David Barker, David Peter Src Computers Inc 4240 N. Nevada Ave Colorado SpringsCO80907 United States SUPERsmith PO Box 2226 SalinasCA93902-2226 United States

ISBN: (纸本)158113293X

SRC Computers, Inc. has integrated adaptive computing into its SRC-6 high-end server, incorporating reconfigurable processors as peers to the microprocessors. Performance improvements resulting from reconfigurable computing can provide orders of magnitude speedups for a wide variety of algorithms. reconfigurable logic in Field Programmable Gate Arrays (fpgas) has shown great advantage to date in special purpose applications and specialty hardware. SRC Computers is working to bring this technology into the general purpose HPC world via an advanced system interconnect and enhanced compiler technology. © 2001 ACM.

关键词： Field programmable gate arrays (FPGA)

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11th International conference on Field-Programmable Logic andapplications 2001

引用

11th International conference on Field-Programmable Logic and applications, FPL 2001

ISBN: (纸本)3540424997

The proceedings contain 74 papers. The special focus in this conference is on Invited Keynote 1 and Architectural Frameworks. The topics include: technology trends and adaptive computing;prototyping framework for reconfigurable processors;an emulator for exploring RaPiD configurable computing architectures;a new placement method for direct mapping into LUT-based fpgas;fGREP - fast generic routing demand estimation for placed FPGA circuits;macrocell architectures for product term embedded memory arrays;gigahertz reconfigurable computing using SiGe HBT BiCMOS fpgas;memory synthesis for FPGA-based reconfigurable computers;implementing a hidden markov model speech recognition system in programmable logic;implementation of (normalised ) RLS lattice on virtex;accelerating matrix product on reconfigurable hardware for signal processing;static profile-driven compilation for fpgas;synthesizing RTL hardware from java byte codes;from behavioral specification to multi-FPGA-prototype;secure configuration of field programmable gate arrays;single-chip FPGA implementation of the advanced encryption standard algorithm;jbits™ implementations of the advanced encryption standard (rijndael );task-parallel programming of reconfigurable systems;chip-based reconfigurable task management;configuration caching and swapping;multiple stereo matching using an extended architecture;implementation of a NURBS to bézier conversor with constant latency;reconfigurable frame-grabber for real-time automated visual inspection (RT-AVI ) systems;processing models for the next generation network;tightly integrated placement and routing for fpgas;a tool for the simultaneous placement and detailed routing of gate-arrays;reconfigurable router modules using network protocol wrappers;development of a design framework for platform-independent networked reconfiguration of software and hardware and the molen ρμ-coded processor.

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reconfigurable media processing

Reconfigurable media processing

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2nd International conference on Information technology - Coding and computing (ITCC 2001)

作者： Dasu, A Panchanathan, S Arizona State Univ Visual Comp & Commun Lab Tempe AZ 85287 USA

ISBN: (纸本)0769510620

Multimedia processing is becoming increasingly important with a range of applications. Existing approaches for processing multimedia data can be broadly classified into two categories, namely (i) Microprocessors with extended media processing capabilities, and (ii) Dedicated implementations (ASICs). The complexity, variety of techniques and tools associated with multimedia processing points to the opportunities for reconfigurable computing devices which will be able to adapt the underlying hardware dynamically in response to changes in the input data or processing environment. This paper proposes a novel approach to design a dynamically reconfigurable processor by performing hardware software co-design for a media processing application. As an example, the analysis of the Shape coding module of MPEG-4 is chosen to demonstrate the potential for reconfigurability.

关键词： Application programs

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