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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

共 418 条记录，以下是381-390 订阅

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Gigahertz reconfigurable computing using SiGe HBT BiCMOS fpgas 11th

引用

11th International conference on Field-Programmable Logic and applications, FPL 2001

作者： Goda, Bryan S. Kraft, Russell P. Carlough, Steven R. Krawczyk, Thomas W. McDonald, John F. United States Military Academy West PointNY10996 United States Rensselaer Polytechnic Institute TroyNY12180 United States IBM Inc PoughkeepsieNY United States Sierra Monolithics Inc Redondo BeachCA90277 United States

ISBN: (纸本)3540424997

Field programmable gate arrays (fpgas) are flexible programmable devices that are used in a wide variety of applications such as network routing, signal processing, pattern recognition and rapid prototyping. Unfortunately, the flexibility of the FPGA hinders its performance due to the additional logic resources required for the programmable hardware. Today s fastest fpgas run in the 250 MHz range. This paper proposes a new family of fpgas utilizing a high-speed SiGe Heterojunction Bipolar Transistor (HBT) design, co-integrated with CMOS in an IBM BiCMOS process. This device is bit-wise compatible with the Xilinx 6200, with operating frequencies in the 1 to 20 GHz range. All logic and routing in this new design is multiplexer based, eliminating the need for pass transistors, the main roadblock to high speed in today s fpgas. © Springer-Verlag Berlin Heidelberg 2001.

关键词： Integrated circuit design

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The systolic ring: A dynamically reconfigurable architecture for embedded systems

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11th International conference on Field-Programmable Logic and applications, FPL 2001

作者： Sassatelli, Gilles Torres, Lionel Galy, Jerome Cambon, Gaston Diou, Camille University of Montpellier II UMR5506 LIRMM 161 Rue ADA Montpellier34392 France

ISBN: (纸本)3540424997

Internet is becoming one of the key features of tomorrow’s communication world. The evolution of mobile phones networks, such as UMTS will soon allow everyone to be connected, everywhere. These new network technologies bring the ability to deal not only with classical voice or text messages, but also with improved content: multimedia. At the mobile level, this kind of data oriented content requires highly efficient architectures;and nowadays mobile system-on-chip solutions will no longer be able to manage the critical constraints like area, power and data computing efficiency. In this paper we will propose a new dynamically reconfigurable network, dedicated to data oriented applications such as the one allowed on third generation networks. Principles, realizations and comparative results will be exposed for some classical applications targeted on different architectures. © Springer-Verlag Berlin Heidelberg 2001.

关键词： Network architecture

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reconfigurable free-space optical interconnection module for pipelined optoelectronic parallel processing

Reconfigurable free-space optical interconnection module for...

引用

conference on Spatial Light Modulators

作者： Ishikawa, M Naruse, M Goulet, A Toyoda, H Kobayashi, Y Univ Tokyo Grad Sch Informat Sci & Technol Dept Informat Phys & Comp Bunkyo Ku Tokyo 1130033 Japan

ISBN: (纸本)0819441716

Optical interconnections and integrated optoelectronic devices are expected to be promising candidates that expand interconnection bandwidth between large-scale integrated circuits (LSIs). We have constructed an optoelectronic parallel computing system that has a reconfigurable free-space parallel optical interconnection module called OCULAR-ii. It has a multi-layer architecture that eliminates the data transfer bottleneck between optoelectronic processing modules by reconfigurable free-space optical interconnections. An optoelectronic processing module is composed of a two-dimensional processing element array where each pixel has its own optical output channel by a VCSEL and optical input channel. The optical interconnection is integrated into a compact module where an optically addressable phase only spatial light modulator and an imaging optical system are compactly fabricated. Each component of the OCULAR-ii system has been designed to be modular and compact. Therefore, just cascading optoelectronic processing modules and optical interconnection modules makes a pipelined parallel processing system. In the optical interconnection module, a custom designed Fourier Transform lens has been used to reduce the working distance of the lens system. A Computer Generated Hologram (CGH) is written on a liquid crystal display (LCD) that is coupled by a fiber optic plate (FOP) to the optically addressable SLM. The interconnection topology between optoelectronic chips is controlled by changing the CGH patterns, which is calculated in advance. A global interconnectivity among processor arrays is also achievable since the communication channels are constructed via optical path in free-space. The data broadcasting between processors that are located spatially far away can be efficiently implemented by free-space optical links in OCULAR-ii's optical interconnection module.

关键词： optical interconnection spatial light modulator reconfigurable optical interconnection parallel processing system pipeline architecture

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4th International conference on Evolvable Systems, ICES 2001

4th International Conference on Evolvable Systems, ICES 2001

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4th International conference on Evolvable Systems: From Biology to Hardware, ICES 2001

ISBN: (纸本)354042671X

The proceedings contain 29 papers. The special focus in this conference is on Evolutionary Design of Electronic Circuits and Embryonic Electronics. The topics include: Two-step incremental evolution of a prosthetic hand controller based on digital logic gates;evolutionary design calibration;implementation of a gate-level evolvable hardware chip;a VLSI implementation of an analog neural network suited for genetic algorithms;initial studies of a new VLSI field programmable transistor array;an embryonics implementation of a self-replicating universal turing machine;asynchronous embryonics with reconfiguration;artificial cells driven by artificial DNA;a self-repairing and self-healing electronic watch;shrinking the genotype;multi-layered defence mechanisms;human-like dynamic walking for a biped robot using genetic algorithm;effect of fitness for the evolution of autonomous robots in an open-environment;incremental evolution of autonomous robots for a complex task;multi-agent robot learning by means of genetic programming;placing and routing circuits on fpgas by means of parallel and distributed genetic programming;a massively parallel architecture for linear machine code genetic programming;self-organized evolutionary process in sets of interdependent variables near the midpoint of phase transition in k-satisfiability;evolutionary optimization of yagi-uda antennas;extraction of design patterns from evolutionary algorithms using case-based reasoning;solving partially observable problems by evolution and learning of finite state machines;polymorphic electronics;initial experiments of reconfigurable sensor adapted by evolution;a lossless compression method for halftone images using evolvable hardware and evolvable optical systems and their applications.

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reconfigurable media processing

Reconfigurable media processing

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International conference on Information technology: Coding and computing (ITCC)

作者： A. Dasu S. Panchanathan Visual Computing and Communications Laboratory Arizona State University USA

ISBN: (纸本)0769510620

Multimedia processing is becoming increasingly important with a range of applications. Existing approaches for processing multimedia data can be broadly classified into two categories, namely: (i) microprocessors with extended media processing capabilities; and (ii) dedicated implementations (ASICs). The complexity, variety of techniques and tools associated with multimedia processing points to the opportunities for reconfigurable computing devices which will be able to adapt the underlying hardware dynamically in response to changes in the input data or processing environment. The paper proposes a novel approach to design a dynamically reconfigurable processor by performing hardware software co-design for a media processing application. As an example, the analysis of the shape coding module of MPEG-4 is chosen to demonstrate the potential for reconfigurability.

关键词： Hardware Graphics Microprocessors Multimedia computing Video compression Transform coding Application software MPEG 4 Standard Animation Speech analysis

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Object oriented meta tools for reconfigurable architectures

Object oriented meta tools for reconfigurable architectures

引用

conference on reconfigurable technology: fpgas for computing and applications ii

作者： Lagadec, L Pottier, B Univ Bretagne Occidentale UFR Sci Brest France

ISBN: (纸本)0819438774

A number of experimental and commercial reconfigurable architectures are designed with various objectives: random logic integration, hardware prototyping, computation accelerators, planar smart sensors or transducers etc Getting a new reconfigurable part to the final user remains a very difficult task, because there are no common tools, nor are there standard models that provides retargeting software development tools. A generic model for reconfigurable circuits has been built in three stages: full implementation of tools for a practical platform, creation of an abstract model and associated tools for arbitrary architectures (programmable editor, geometric operations on physical modules. place and route), description tools for concrete architecture defined as a specialization of the abstract model. Main advantages and further fields of research based on this approach are: retargetable tools based on a description of the new architecture with possibility to embed new primitives, possibility of a quantitative approach in the design of new reconfigurable architectures.

关键词： reconfigurable prototyping modelization

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Framework for architecture-independent run-time reconfigurable applications

Framework for architecture-independent run-time reconfigurab...

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conference on reconfigurable technology: fpgas for computing and applications ii

作者： Lehn, DI Hudson, RD Athanas, PM Virginia Tech Bradley Dept Elect & Comp Engn Blacksburg VA 24061 USA

ISBN: (纸本)0819438774

Configurable computing Machines (CCMs) have emerged as a technology with the computational benefits of custom ASICs as well as the flexibility and reconfigurability of general-purpose microprocessors. Significant effort from the research community has focused on techniques to move this reconfigurability from a rapid application development tool to a run-time tool. This requires the ability to change the hardware design while the application is executing and is known as Run-Time Reconfiguration (RTR). Widespread acceptance of run-time reconfigurable custom computing depends upon the existence of high-level automated design tools. Such tools must reduce the designers effort to port applications between different platforms as the architecture, hardware, and software evolves. A Java implementation of a high-level application framework, called Janus, is presented here. In this environment, developers create Java classes that describe the structural behavior of an application. The framework allows hardware and software modules to be freely mixed and interchanged. A compilation phase of the development process analyzes the structure of the application and adapts it to the target platform. Janus is capable of structuring the run-time behavior of an application to take advantage of the memory and computational resources available.

关键词： RTR run-time reconfiguration CCM configurable computing FPGA automated design

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Hardware based image processing library for Virtex FPGA

Hardware based image processing library for Virtex FPGA

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conference on reconfigurable technology: fpgas for computing and applications ii

作者： Gorgon, M Tadeusiewicz, R Stanislaw Staszic Univ Min & Met Biocybernet Lab PL-30059 Krakow Poland

ISBN: (纸本)0819438774

The payer considers hardware-based realization of image processing algorithms. Usage of single FPGA device - Virtex as a processing element capable to carry out image processing in real-time is thoroughly discussed. For implementation of the algorithms in hardware resources specialized IP cores architectures has been designed and tested, The image-processing library consists of individual cores able to be linked together on a software level and implemented in high capacity FPGA devices is proposed.

关键词： image processing real-time FPGA IP-cores re-configurable computing

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Parallel k-mismatching of strings using daughter-board structure

Parallel k-mismatching of strings using daughter-board struc...

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conference on reconfigurable technology: fpgas for computing and applications ii

作者： Plaks, TP S Bank Univ SCISM London SE1 0AA England

ISBN: (纸本)0819438774

This paper presents a family of scalable regular array structures for k-mismatches problem of a reference string of length n and a pattern of length n. The conventional regular array of size O(m) computes in O(n + m). The drawback of his solution is, first, that the performance is bounded by the length of pattern, and second;the long latency. In this paper we present regular array solutions where the array size is parameterized by the number, delta. 1 less than or equal to delta less than or equal ton, of parallel input/output channels. The array of size O(sm) computes in O(n/s + m) time. In order to reduce the latency time, tree-like structures for computing reduction are used, reducing the time complexity to O(n/s+ m (1/r)), r is the dimensionality of array. The number of patterns can be l, while the time complexity increases to O(n/s + m(1/r) + l) using O(sml) processors. Proposed regular arrays are suitable for teal-time applications and are efficiently mapped onto fpgas using daughter-board structure.

关键词： mismatching strings regular arrays fpgas

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Debug of reconfigurable systems

Debug of reconfigurable systems

引用

conference on reconfigurable technology: fpgas for computing and applications ii

作者： Price, T Levi, D Guccione, SA Xilinx Inc San Jose CA 95124 USA

ISBN: (纸本)0819438774

While FPGA design tools have progressed steadily, availability of tools to aid in debug of FPGA-based systems has lagged. In particular, support for debug of run-time reconfigurable (RTR) systems have been all but absent. In this paper we describe DDTScript, a scripting language to aid in design, debug and test of RTR systems. The DDTScript language is fully integrated with the BoardScope(TM) graphical debug tool and permits parameterization, instantiation, and removal of Run-time Parameterizable (RTP) Cores and other configurable circuit components. DDTScript also provides control of system level resources and supplies access to device state and configuration data. DDTScript is currently used not only to test and debug RTP Cores, but to construct and interact with complete designs. DDTScript is currently part of the JBits(TM) tool suite and supports the Xilinx Virtex(TM) family of FPGA devices.

关键词： debug regression testing run-time reconfiguration virtex script FPGA

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