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37th IEEE International conference on Data Engineering (IEEE ICDE)

作者： Lekshmi, B. G. Meyer-Wegener, Klaus Friedrich Alexander Univ Data Management CS6 Erlangen Germany

ISBN: (纸本)9781665448901

Placing the processing power near the data, rather than shipping the data to the processor is inevitable and demanding in the era of Big Data. Thereby near-data processors gained much attention in recent years as they can reduce the massive data transfer between data sources and computing nodes. However, it is important to rethink the computing architecture to achieve the maximum advantage of near-data-processing technology, particularly for query-processing applications. In this paper, we propose a new approach to the query optimization in a relational DBMS, which considers the specialized computing capabilities of the attached FPGA-based near-data processors. The paper focuses on the hardware-conscious optimization using extended rules and cost models as well as on refining the optimization strategies for changes in the hardware state of execution. Our evaluations demonstrate that the proposed query-optimization approach can improve the processing of queries using near-data processors based on fpgas.

关键词： Query optimization FPGA Near-data processor Hardware capability

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UNILOGIC: A Novel Architecture for Highly Parallel reconfigurable Systems

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ACM TRANSACTIONS ON reconfigurable technology AND SYSTEMS 2020年第4期13卷 1–32页

作者： Ioannou, Aggelos D. Georgopoulos, Konstantinos Malakonakis, Pavlos Pnevmatikatos, Dionisios N. Papaefstathiou, Vassilis D. Papaefstathiou, Ioannis Mavroidis, Iakovos Tech Univ Crete Sch ECE Iraklion 73100 Greece Telecommun Syst Inst Iraklion 73100 Greece Fdn Res & Technol Hellas FORTH N Plastira 100 Iraklion 70013 Greece Synelixis Solut Chalkida Greece Natl Tech Univ Athens Sch ECE Athens Greece Chalmers Univ Technol Comp Sci & Engn Gothenburg Sweden Aristotle Univ Thessaloniki Sch ECE Thessaloniki Greece

One of the main characteristics of High-performance computing (HPC) applications is that they become increasingly performance and power demanding, pushing HPC systems to their limits. Existing HPC systems have not yet reached exascale performance mainly due to power limitations. Extrapolating from today's top HPC systems, about 100-200 MWatts would be required to sustain an exaflop-level of performance. A promising solution for tackling power limitations is the deployment of energy-efficient reconfigurable resources (in the form of Field-programmable Gate Arrays (fpgas)) tightly integrated with conventional CPUs. However, current FPGA tools and programming environments are optimized for accelerating a single application or even task on a single FPGA device. In this work, we present UNILOGIC (Unified Logic), a novel HPC-tailored parallel architecture that efficiently incorporates fpgas. UNILOGIC adopts the Partitioned Global Address Space (PGAS) model and extends it to include hardware accelerators, i.e., tasks implemented on the reconfigurable resources. The main advantages of UNILOGIC are that (i) the hardware accelerators can be accessed directly by any processor in the system, and (ii) the hardware accelerators can access any memory location in the system. In this way, the proposed architecture offers a unified environment where all the reconfigurable resources can be seamlessly used by any processor/operating system. The UNILOGIC architecture also provides hardware virtualization of the reconfigurable logic so that the hardware accelerators can be shared among multiple applications or tasks. The FPGA layer of the architecture is implemented by splitting its reconfigurable resources into (i) a static partition, which provides the PGAS-related communication infrastructure, and (ii) fixed-size and dynamically reconfigurable slots that can be programmed and accessed independently or combined together to support both line and coarse grain reconfiguration.(1) Finally,

关键词： Accelerators partial reconfiguration FPGA unification prototyping

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Flexible and Efficient Implementation of CRYSTALS-KYBER SIMD RISC-V Coprocessor Based on Customized Vector Instruction-Set Extension 19

Flexible and Efficient Implementation of CRYSTALS-KYBER SIMD...

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19th IEEE Asian Solid-State Circuits conference, A-SSCC 2023

作者： Zhang, Jiaming Lu, Jiahao Liu, Dongsheng Li, Aobo Li, Xiang Yang, Shuo Hu, Ang Zou, Xuecheng Huazhong University of Science and Technology China

ISBN: (纸本)9798350330038

With the development of quantum computers in recent years, the security of traditional public-key encryption algorithms is facing serious threats, and post-quantum cryptography (PQC) algorithms that can resist quantum computer attacks are urgently needed. CRYSTALS-KYBER as the finalized NIST key-encapsulation scheme, is continuously advancing the standardization process. The existing hardware implementations of Kyber mostly use compact architectures to pursue high speed and high performance with the cost of programmability, while most hardware-software co-designs suffer from low parallelism and performance. Aiming at flexibly and efficiently implementing the key encapsulation mechanism (KEM) of Kyber, this work presents a single instruction multiple data (SIMD) Kyber coprocessor that supports the RISC-V instruction-set. A reconfigurable polynomial and logic unit (PLU) is designed, which can accelerate all types of polynomial vector instruction operations, and a dynamic hardware scheduling strategy is proposed to enable different types of instructions to be executed parallelly, improving the coprocessor pipeline throughput. Implemented on the Ultrascale+ FPGA platform and evaluated under SMIC 40nm technology, the proposed coprocessor achieves the fastest computing speed with the lowest power consumption and 3.5×/6.2× improvement in FPGA/ASIC AT product efficiency. © 2023 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Lightweight ANU-ii Implementation on FPGA

Lightweight ANU-II Implementation on FPGA

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IEEE Distributed computing, VLSI, Electrical Circuits and Robotics (DISCOVER)

作者： Thrapthi Shetty Kiran Kumar V G Mohan Singh Khati Sandesh Deeptha Suresh A Rasim Musthafa Department of Electronics and Communication Engineerng A J Instittue of Engineering and Technology Kottara Mangaluru India

ISBN: (数字)9798350350593

ISBN: (纸本)9798350350609

As the application of Embedded devices in network communication increases exponentially, there is a growing necessity for effective security mechanisms that may be implemented within resource constraints. Lightweight cryptography becomes an essential solution, which includes constraints like latency, memory size, area, and power consumption. This study presents a hardware implementation of the ANU-ii and Modified ANU-ii block cipher using SPARTAN-6 Field Programmable Gate Arrays (fpgas). The design presented has a 64-bit ANU-ii and Modified ANU-ii block cipher and offers comparison analysis with alternative data path architectures according to various design parameters. The FPGA-based solution additionally be reconfigured and is flexible, thereby making it appropriate for a variety of applications that require secure data transmission. The results demonstrate that the ANU-ii and Modified ANU-ii block cipher is not only high-performing but also flexible to various system needs. This research indicates how well our suggested encryption design may address the demands of current security concerns related to data. The result of the proposed ANU-ii and Modified ANU-ii algorithm shows a maximum frequency of 313.686 MHz and 316.131 MHz and delay of 3.188 ns and 3.163 ns respectively.

关键词： Measurement Ciphers Power demand Memory management Very large scale integration Logic gates Encryption Iterative methods Field programmable gate arrays Robots

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A reconfigurable Architecture to Implement Linear Transforms of Image Processing applications

A Reconfigurable Architecture to Implement Linear Transforms...

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International conference on Frontiers in computing and Systems, COMSYS 2020

作者： Sanyal, Atri Sinha, Amitabha Amity Institute of Information Technology Amity University Kolkata Major Arterial Road Action Area II Rajarhat New Town Kolkata India Institute of Micro Electronics and VLSI Technology Maulana Abul Kalam Azad University of Technology West Bengal BF Block Sector 1 Bidhannagar Kolkata700064 India

ISBN: (纸本)9789811578335

A reconfigurable architecture capable of implementing flow graph-based computationally intensive image processing transforms is introduced. The conceptual design of the architecture is deduced using a graph theoretical approach. The graph theoretical model is transformed into a reconfigurable design. The design of the overall architecture as well as the design of the processing element is implemented in VHDL using Xilinx Vivado. The architecture is synthesized. The result is presented in terms of size and timing behaviour. The processing elements inside the architecture are simulated by a test bench program executing two major operations to see the possibility of further improvement of the design. Future direction of the research is discussed. © 2021, Springer Nature Singapore Pte Ltd.

关键词： Graphic methods

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FAWS: FPGA Acceleration of Large-Scale Wave Simulations

FAWS: FPGA Acceleration of Large-Scale Wave Simulations

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International conference on Application Specific Systems (ASAP), Architectures and Processors

作者： Dimitrios Gourounas Bagus Hanindhito Arash Fathi Dimitar Trenev Lizy K. John Andreas Gerstlauer The University of Texas at Austin Austin TX USA ExxonMobil Technology and Engineering Annandale NJ USA

Efficiently solving large-scale scientific problems described by partial differential equations (PDEs) is a critical task in high-performance computing. Application-specific hardware design is a well-known solution, but the wide range of kernels makes it infeasible to provision supercomputers with accelerators for all applications. This makes reconfigurable platforms a promising direction. In this work, we focus on wave simulations using discontinuous Galerkin solvers, as an important class of PDE applications. Existing work using fpgas is limited to accelerating specific kernels or small problems that fit into FPGA BRAM. We present FAWS, a generic and configurable architecture for large-scale accelerated wave simulation problems running on fpgas out of DRAM. FAWS exploits fine- and coarse-grain parallelism using a scalable array of application-specific processing cores, and incorporates novel dataflow optimizations, including prefetching, kernel fusion, and memory layout optimizations to minimize data transfers and maximize DRAM bandwidth utilization. We demonstrate FAWS on the simulation of elastic wave equations. Results show that a single FPGA core achieves 2.2x higher performance than 24 Xeon cores with 18.64x better energy efficiency, when given ~1.94x less peak DRAM bandwidth. Scaling to the same peak DRAM bandwidth, an FPGA is 4.27x and 1.96x faster than 24 CPU cores and an Nvidia P100 GPU, with 31.33x and 5.29x better efficiency, respectively.

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UNILOGIC: A novel architecture for highly parallel reconfigurable systems

UNILOGIC: A novel architecture for highly parallel reconfigu...

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ACM Transactions on reconfigurable technology and Systems

作者： Ioannou, Aggelos D. Georgopoulos, Konstantinos Malakonakis, Pavlos Pnevmatikatos, Dionisios N. Papaefstathiou, Vassilis D. Papaefstathiou, Ioannis Mavroidis, Iakovos School of ECE Technical University of Crete Telecommunication Systems Institute Crete Greece Telecommunication Systems Institute Chania Greece Chalmers University of Technology Gothenburg Sweden School of ECE Aristotle University of Thessaloniki Thessaloniki Greece

关键词： reconfigurable hardware Computation theory Computer hardware Energy efficiency Field programmable gate arrays (FPGA) Memory architecture Parallel architectures Program processors reconfigurable architectures Signal receivers System on chip Communication infrastructure Hardware virtualization High performance computing (HPC) Partitioned Global Address Space Programming environment Proposed architectures reconfigurable resources reconfigurable systems

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Possibilities and Challenges for reconfigurable Hardware and Cloud Architectures in Data-Intensive Scientific applications 7

Possibilities and Challenges for Reconfigurable Hardware and...

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7th International conference on Software Defined Systems, SDS 2020

作者： Bawatna, Mohammed Knodel, Oliver Spallek, Rainer G. Institut für Technische Informatik Technische Universität Dresden Dresden Germany Helmholtz Zentrum Dresden Rossendorf Department of Computational Science Dresden Germany

ISBN: (纸本)9781728172194

Advances in process technology and new design tools have expanded the scope of embedded systems. This ranges from the implementation in several chips on board to module groups in integrated circuits. reconfigurable hardware and, in particular, fpgas are used more frequently in scientific applications, where they enable the development of complex and intelligent field devices. Furthermore, this increased the use of a platform-based design approach that facilitates the development and verification of complex fpgas through the full reuse of hardware and software modules. Especially in the area of heterogeneous accelerators, which can improve the exploitation of modern data centers. Another critical aspect in the evolution of embedded systems is the trend towards networking embedded nodes using specialized computational and networking technologies called cloud computing. In this paper, we will present our data-intensive experiments at the terahertz source at ELBE accelerator-based light source, and its integration into a reproducible data management workflow at the heterogeneous cluster in our data centre. © 2020 IEEE.

关键词： reconfigurable hardware

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FPGA Architecture To Enhance Hardware Acceleration for Machine Learning applications

FPGA Architecture To Enhance Hardware Acceleration for Machi...

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International conference on computing Methodologies and Communication (ICCMC)

作者： Anirudh Itagi S Krishvadana K P Bharath M Rajesh Kumar Alumni School of Electronics Engineering Vellore Institute of Technology Vellore TN School of Electronics Engineering Vellore Institute of Technology Vellore TN

Many algorithms have been developed in the field of Machine learning and its sub-fields such as neural networks, Deep learning and so on, for applications such as pattern classification, image and video processing, statistical data mining and so forth. These algorithms perform such tasks with remarkable accuracy. However, when implemented in traditional processor core software, many of these algorithms get choked when the size of the network or computational demand of the algorithm scales up. fpgas and ASICs offer higher computation capability, throughput and bandwidth. Features such as massive parallel processing, high performance and reliability, are strong arguments for fpgas for Deep Neural Network applications. fpgas offer reconfigurable, flexible architectures where even the most popular GPUs fall short. This paper proposes a robust, re-configurable architecture for deploying Machine learning algorithms and presents its advantages by implementing a Neural Network in an FPGA and comparing its results with an implementation in a Raspberry Pi.

关键词： Machine learning algorithms Software algorithms Neural networks Computer architecture Throughput Software Classification algorithms

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COPRAO: A Capability Aware Query Optimizer for reconfigurable Near Data Processors

COPRAO: A Capability Aware Query Optimizer for Reconfigurabl...

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International conference on Data Engineering Workshops

作者： B. G. Lekshmi Klaus Meyer-Wegener Data Management (CS6) Friedrich-Alexander-Universität Erlangen Germany

关键词： conferences Query processing Refining Computer architecture Data transfer Data engineering Hardware

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