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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

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Fast scheduling and placement methods for C to hardware/software compilation

Fast scheduling and placement methods for C to hardware/soft...

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conference on reconfigurable technology: fpgas for computing and applications ii

作者： Bazargan, K Sarrafzadeh, M Univ Minnesota Dept Elect & Comp Engn Minneapolis MN 55455 USA

ISBN: (纸本)0819438774

Advances in the FPGA technology, both in terms of device capacity and architecture, have resulted in introduction of reconfigurable computing machines, where the hardware adapts itself to the running application to gain speedup. To keep up with the ever-growing performance expectations of such systems, designers need new methodologies and tools for developing reconfigurable computing systems (RCS). This paper addresses the need for fast compilation and physical design phase to be used in application development/debugging/testing cycle for RCS. We present a high-level synthesis approach that is integrated with placement, hence making the compilation cycle much faster. On the average, our tool generates the VHDL code (and the corresponding placment information) from the data flow graph of a program in less than a minute. By losing 1.3 times in the quality of the design, we can achieve, 10.7 times speedup in the Xilinx placement phase, and 2.5 times overall speedup in the Xilinx place-and-route phase.

关键词： compilation recnfigurable computing system high-level synthesis physical design design automation

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Compiler for a dynamically reconfigurable processor with cell array structures

Compiler for a dynamically reconfigurable processor with cel...

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reconfigurable technology: fpgas for computing and applications ii

作者： Hatano, Fumihiro Morishita, Takayuki Komoku, Kiyotaka Teramoto, Iwao Okayama Prefectural Univ Okayama Japan

Our processor is featured by the architecture such that the configuration can be dynamically and optimally rearranged in real-time. We have already developed the instruction sets, the emulation and debug programs for the present processor, utilizing circuit designs. This paper described a newly developed compiler as the alternative to that using the circuit designs.

关键词： Program compilers

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XVPI: A portable hardware/software interface for Virtex

XVPI: A portable hardware/software interface for Virtex

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conference on reconfigurable technology: fpgas for computing and applications ii

作者： Sundararajan, P Guccione, SA Xilinx Inc San Jose CA 95124 USA

ISBN: (纸本)0819438774

XVPI, the Xilinx Virtex Portable Interface, is a hardware / software interface and specification to assist, in the design and implementation of Xilinx Virtex(TM) based systems. XVPI specifies a software accessible register to be defined in the hardware. This register contains all of the control and data signals necessary to drive the Virtex device. The software supplied with XVPI uses this register to read and write control and data signals to perform various device level functions. These functions combine to produce an Application Program Interface (API) which provides access to the Virtex device from software. The XVPI API supports all of the device level operations including partial configuration download, partial configuration readback, clock control and reset. Once the system is operational, designers may replace the software routines in the XVPI API with hardware assisted routines. This increases the system performance incrementally, without affecting the functionality. Though specified for the Virtex based system, this technique to perform the device level functions from software can be applied to any FPGA device. Additionally XVPI is also supplied with an interface supporting Xilinx's JBits toolkit. Once XVPI implemented, JBits and its associated applications. including the BoardScope debug tool, are fully operational on that Virtex based system.

关键词： reconfigurable systems FPGA hardware/software co-design

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Application of a dynamically reconfigurable cell-array processor to an MPEG-2 video decoder

Application of a dynamically reconfigurable cell-array proce...

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conference on reconfigurable technology: fpgas for computing and applications ii

作者： Komoku, K Hatano, F Morishita, T Teramoto, I Okayama Prefectural Univ Fac Comp Sci & Syst Engn Okayama 7191197 Japan

ISBN: (纸本)0819438774

We have proposed and developed the Dynamically reconfigurable Cell-Array Processor (DRCAP) that consists of functional Cell Arrays (CAs), and buses/bus-switches that provide with connections between CAs. A software simulator of the DRCAP is constructed, on which the MPEG-2 video decoder is successfully implemented. This MPEG-2 decoder dynamically changes the configuration in many times during the decoding process. The processing is executed every macro-block, reconfiguring in each component process of the MPEG-2 decoding such as the variable length decoding, the dequantization. the inverse DCT, and so on. The resources required for the DRCAP to decode the MPEG-2 MP@ML video stream is investigated. In the simulation it is found that the numbers of CAs to decode the MPEG-2;MP@ML video stream are 8 for PCAs, 1 for LCA, 2 for CCAs and 35 for MCAs, and the execution cycle required is 94.6MHz. In the case of doubling all configurations, where the same two processes are executed in parallel, the numbers of CAs are 15, 1, 4 and 69, for PCA, LCA, CCA and MCA, respectively, and the execution frequency of 55.9MHz is required.

关键词： dynamically reconfigurable processor MPEG-2 decoder MPEG-2 video stream MP@ML cell-array architecture parallel processing

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Programming method and a management unit in a reconfigurable processor with cell array structure for general purpose calculation

Programming method and a management unit in a reconfigurable...

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reconfigurable technology: fpgas for computing and applications ii

作者： Morihsita, Takayuki Komoku, Kiyotaka Hatano, Fumihiro Teramoto, Iwao Okayama Prefectural Univ Okayama Japan

We have been developing a parallel processor that it is possible to reconfigure to realize a general-purpose computation at very high speed. This reconfiguration changes a kind of and a number of processing elements and connection between processing elements at real time. In this paper, we extend circuit design technique to describing a dynamically reconfiguration of circuit component and propose a management unit in a reconfigurable processor necessary for executing a program. Finally, we examine a performance of this processor by using an example program.

关键词： Parallel processing systems

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Effect of data truncation in an implementation of pixel clustering on a custom computing machine

Effect of data truncation in an implementation of pixel clus...

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conference on reconfigurable technology: fpgas for computing and applications ii

作者： Leeser, M Theiler, J Estlick, M Kitaryeva, N Szymanski, JJ Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA

ISBN: (纸本)0819438774

We investigate the effect of truncating the precision of hyperspectral image data for the purpose of more efficiently segmenting the image using a variant of k-means clustering We describe the implementation of the algorithm an field-programmable gate array (FPGA) hardware. Truncating the data to only a few bits per pixel in each spectral channel permits a more compact hardware design, enabling greater parallelism, and ultimately a more rapid execution. It also enables the storage of larger images in the onboard memory. In exchange for faster clustering, however, one trades off the quality of the produced segmentation. We find, however, that the clustering algorithm can tolerate considerable data truncation with little degradation in cluster quality. This robustness to truncated data can be extended by computing the cluster centers to a few more bits of precision than the data. Since there are so many more pixels than centers, the more aggressive data truncation leads to significant gains in the number of pixels that can be stored in memory and processed in hardware concurrently.

关键词： hyperspectral k-means image segmentation image processing field-programmable gate array (FPGA)

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Approach to constructing reconfigurable computer vision system

Approach to constructing reconfigurable computer vision syst...

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reconfigurable technology: fpgas for computing and applications ii

作者： Xue, Jianru Zheng, Nanning Wang, Xiaoling Zhang, Yongping Xi'an Jiaotong Univ Xi'an China

In this paper, we propose an approach to constructing reconfigurable vision system. We found that timely and efficient execution of early tasks can significantly enhance the performance of whole computer vision tasks, and abstract out a set of basic, computationally intensive stream operations that may be performed in parallel and embodies them in a series of specific front-end processors. These processors based on fpgas (Field programmable gate arrays) can be re-programmable to permit a range of different types of feature maps, such as edge detection & linking, image filtering. Front-end processors and a powerful DSP constitute a computing platform, which can perform many computer vision tasks. Additionally we adopt the focus-of-attention technologies to reduce the I/O and computational demands by performing early vision processing only within a particular region of interest. Then we implement a multi-page, dual-ported image memory interface between the image input and computing platform (including front-end processors, DSP). Early vision features were loaded into banks of dual-ported image memory arrays, which are continually raster scan updated at high speed from the input image or video data stream. Moreover, the computing platform can be completely asynchronous, random access to the image data or any other early vision feature maps through the dual-ported memory banks. In this way, the computing platform resources can be properly allocated to a region of interest and de-coupled from the task of dealing with a high speed serial raster scan input. Finally, we choose PCI bus as the main channel between the PC and computing platform. Consequently, front-end processors' control registers and DSP's program memories were mapped into the PC's memory space, which provides users with the access to reconfigure the system at any time. We also present test result of a computer vision application based on the system.

关键词： Computer vision

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Building a flexible trigger system for high energy physics

Building a flexible trigger system for high energy physics

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conference on reconfigurable technology: fpgas for computing and applications ii

作者： Cussans, DG Newbold, DM Heath, GP Brooke, JJ Maddox, J Univ Bristol Bristol BS8 1TL Avon England

ISBN: (纸本)0819438774

In the 17(th) century Sir Isaac Newton wrote "These are therefore the agents in Nature able to make the Particles of Bodies ftick together by very ftrong Attractions: And it is the Bufinefs of Experimental Philofophy to find them out". In the 21(st) century the Large Hadron Collider (LHC)I continues that "business''. Bunches of protons will be accelerated to all energy of 7TeV/c per proton* around a 27km circumference ring buried underneath French/Swiss countryside near Geneva. At a number of points around the ring counter-rotating bunches of protons will be passed through each other. Some of the protons will interact violently and the new particles generated will fly outwards into detectors surrounding the interaction region. Typically these detectors have millions of channels and data flows out of the "front-end" at about 400EBytes/year(dagger). Data can only he stored at about 1PByte/year, a factor of 4 x 10(5) less. Fortunately most interactions involve physical processes that are already understood and a multi-level trigger system is used to select data fr om interesting or unexpected events. This paper describes the Global Calorimeter Trigger (GCT),(2) part of the trigger system for the Compact, Muon Solenoid (CMS)(3,4) detector at the LHC.

关键词： high energy physics large hadron collider (LHC) compact muon solenoid (CMS) trigger reconfigurable FPGA xilinx

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Study of high-performance reconfigurable constant coefficient multiplier implementations

Study of high-performance reconfigurable constant coefficien...

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reconfigurable technology: fpgas for computing and applications ii

作者： James-Roxby, Philip Blodget, Brandon J. Xilinx Inc Boulder United States

The use of dynamic reconfiguration appears extremely attractive for implementing adaptive processing algorithms. Often, the adaption involves updating look-up tables based on a parameter which can only be determined at run-time. For reasons of efficiency, these look-up tables are read-only to the rest of the circuitry. This paper compares the use of run-time reconfiguration and read-only look-up tables, with similar implementations using writable memories. The application under consideration is the multi-layer perceptron neural network. It is shown that the ROM based network is considerably simpler than the RAM based network, at the expense of a dramatically increased time to update the weights during training.

关键词： Multilayer neural networks

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Static and dynamic reconfigurable designs for a 2D shape-adaptive DCT 10th

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10th International conference on Field-Programmable Logic and applications, FPL 2000

作者： Gause, Jörn Cheung, Peter Y. K. Luk, Wayne Department of Electrical and Electronic Engineering Imperial College of Science Technology and Medicine LondonSW7 2BT United Kingdom Department of Computing Imperial College of Science Technology and Medicine LondonSW7 2AZ United Kingdom

ISBN: (纸本)3540678999

This paper presents two reconfigurable design approaches for a two dimensional Shape-Adaptive Discrete Cosine Transform (2D SA-DCT). The SA-DCT is an example of a new type of multimedia video processing algorithm where the computations performed are data dependent. A static design, where the configuration does not change during execution of the task, is presented. The use of a data dependence graph (DDG) is proposed which represents the computations and input signals required to calculate a particular output signal depending on a variable input parameter. By re-structuring the DDG and exploiting possible sharing of FPGA resources for different entities within the SA-DCT, it is demonstrated that the area required for an implementation can be significantly reduced. An alternative dynamic approach is also introduced where the FPGA’s configuration may change over time. This is well suited to using dynamically reconfigurable logic but suffers from long reconfiguration time if current fpgas are used. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Field programmable gate arrays (FPGA)

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