检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

408 篇 会议
9 篇 期刊文献
1 篇 学位论文

馆藏范围

418 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

221 篇 工学
- 210 篇 计算机科学与技术...
- 100 篇 软件工程
- 49 篇 电气工程
- 49 篇 电子科学与技术（可...
- 22 篇 控制科学与工程
- 17 篇 信息与通信工程
- 12 篇 动力工程及工程热...
- 7 篇 土木工程
- 5 篇 光学工程
- 5 篇 建筑学
- 5 篇 航空宇航科学与技...
- 5 篇 生物工程
- 4 篇 机械工程
- 4 篇 环境科学与工程（可...
- 3 篇 仪器科学与技术
- 2 篇 生物医学工程（可授...
66 篇 理学
- 39 篇 数学
- 17 篇 物理学
- 6 篇 生物学
- 6 篇 系统科学
- 4 篇 统计学（可授理学、...
- 2 篇 化学
- 1 篇 地球物理学
- 1 篇 地质学
13 篇 管理学
- 13 篇 管理科学与工程(可...
- 9 篇 工商管理
3 篇 经济学
- 3 篇 应用经济学
3 篇 医学
- 3 篇 临床医学
2 篇 教育学
- 2 篇 教育学
1 篇 法学
- 1 篇 社会学

主题

149 篇 field programmab...
96 篇 hardware
69 篇 computer archite...
35 篇 field programmab...
32 篇 application soft...
32 篇 fpga
24 篇 reconfigurable a...
20 篇 runtime
20 篇 acceleration
19 篇 parallel process...
19 篇 reconfigurable c...
16 篇 routing
16 篇 digital signal p...
15 篇 high performance...
14 篇 concurrent compu...
14 篇 reconfigurable l...
14 篇 random access me...
14 篇 clocks
12 篇 bandwidth
12 篇 microprocessors

机构

7 篇 department of co...
5 篇 george washingto...
4 篇 institute for re...
3 篇 rochester instit...
3 篇 george mason uni...
3 篇 karlsruhe instit...
3 篇 xilinx inc san j...
2 篇 heinz nixdorf in...
2 篇 chengdu universi...
2 篇 northeastern uni...
2 篇 brocade communic...
2 篇 department of el...
2 篇 institute of com...
2 篇 embedded softwar...
2 篇 department of el...
2 篇 variel microelec...
2 篇 institut für tec...
2 篇 institute for se...
2 篇 faculty of elect...
2 篇 department of el...

作者

9 篇 luk wayne
6 篇 wayne luk
4 篇 cheung peter y. ...
4 篇 axel jantsch
4 篇 zhonghai lu
4 篇 t. el-ghazawi
4 篇 ming liu
4 篇 peter y. k. cheu...
4 篇 wolfgang kuehn
3 篇 s.j. visser
3 篇 david kearney
3 篇 sonia lopez
3 篇 a.s. dawood
3 篇 j.a. williams
3 篇 john wawrzynek
3 篇 e. el-araby
3 篇 sven-ole voigt
3 篇 shaoyi cheng
3 篇 w. luk
3 篇 prasanna viktor ...

语言

411 篇 英文
7 篇 其他

检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

共 418 条记录，以下是401-410 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

High bandwidth and low latency from a three-dimensional reconfigurable interconnect

High bandwidth and low latency from a three-dimensional reco...

引用

conference on reconfigurable technology - fpgas for computing and applications

作者： Morris, J Tham, S Univ Western Australia Ctr Intelligent Informat Proc Syst Nedlands WA 6907 Australia

ISBN: (纸本)081943437X

A high bandwidth, low latency processor interconnect has been constructed using off-the-shelf fpgas and a small amount of additional logic. The Achilles system comprises a router in which the main circuit elements (the fpgas) have been placed on ten small PCBs and connected together to make a router 'stack' and a PCI interface. On the first prototype, channel bandwidth has been measured at 28Mbytes/second and latency was measured to be 800ns. The newer low-voltage fpgas will be used in the next Achilles variant, allowing the bandwidth capability will increase to close to the theoretical maximum for PCI bus. The router stack and PCI interface also has application as a general purpose reconfigurable processor which may be arbitrarily extended by adding further stacks to the system.

关键词： processor interconnect circuit switching reconfigurable computing

来源：评论

学校读者我要写书评

暂无评论

Combined temporal partitioning and scheduling for reconfigurable architectures

Combined temporal partitioning and scheduling for reconfigur...

引用

conference on reconfigurable technology - fpgas for computing and applications

作者： Pandey, A Vemuri, R Univ Cincinnati Dept ECECS Lab Digital Design Environm Cincinnati OH 45221 USA

ISBN: (纸本)081943437X

Dynamically reconfigurable processors are becoming increasingly viable with the advent of modern field-programmable devices. A key feature of dynamically reconfigurable fpgas is that the logic, and interconnect is time-multiplexed, This enables the implementation of large circuits by partitioning the specification into multiple segments, that execute one after the other on the reconfigurable processor. The available resources can be reused which gives us virtually an infinite pool of resources. In this paper, we introduce a novel technique of temporal partitioning and synthesis of behavioral specification for reconfigurable architectures. We try to optimize the overall latency by performing a trade-off between the total number of partitioned segments, and the latency of each segment. Our approach integrates partitioning and scheduling, and performs design space exploration to exploit the trade-off. We also introduce an enhanced Force-Directed List Scheduling (FDLS) algorithm to perform partitioning. We demonstrate the effectiveness of our approach with experimental results.

关键词： Field programmable gate arrays Chemical elements Computer aided design Logic Performance modeling reconfigurable computing computing systems Computer programming Fourier transforms Process modeling

来源：评论

学校读者我要写书评

暂无评论

Quick Qard technology: Hardware object oriented use and RC management system

Quick Qard Technology: Hardware object oriented use and RC m...

引用

conference on reconfigurable technology - fpgas for computing and applications

作者： Ledzius, RC Maturo, L Quickflex Inc. (United States) Renaissance Worldwide Inc. (United States)

ISBN: (纸本)081943437X

QUICKFLEX's patent pending and revolutionary Quick Qard technology (QQT) reconfigurable computing (RC) architecture approaches RC from an Operating System (OS) systems viewpoint, rather than from the perspective of any one particular application. As such, many problems important to integrating reconfigurable logic into the OS are solved These problems would otherwise prevent RC from easily being used in a general-purpose mainstream market. The differences between QQT and other RC board methods of use is not so much in the RC hardware and boards, but in the way the RC hardware is utilized as part of a system. Advantages of the Quick Qard technology (QQT) system of use for RC include a common RC Driver operating system interface for any RC board (regardless of FPGA type, board vendor, or board embodiment), hardware object independence allowing standardization of hardware object functions, resource management of RC resources and configurations, concurrent multi-application sharing of RC resources (even for multiple asynchronous interrupts on a single board), low overhead and efficient interfacing, and ease of use. Implemented and demonstrated in a portable embodiment (PCMCIA PC-Card), the problems addressed by this solution have been often ignored and they are the most important ones to solve if RC is ever to migrate into mainstream computing.

关键词： RC reconfigurable computing method portable hardware objects Quick Qard technology

来源：评论

学校读者我要写书评

暂无评论

Adaptive motor control with reconfigurable logic

Adaptive motor control with reconfigurable logic

引用

conference on reconfigurable technology - fpgas for computing and applications

作者： Leeser, M Matulis, K Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA

ISBN: (纸本)081943437X

We describe the design and implementation of a speed feedback module for an adaptive motor control system. This system is innovative in its use of reconfigurable logic to accurately measure the speed of a motor. The speed of a motor is calculated as the derivative of the position with respect to time (dQ/dt). The position is calculated from information provided by the rotor and the stator. There are a fixed number of positions marked off on the rotor. Each time the rotor mark passes a fixed position on the stator, a pulse is generated. A discrete approximation to the speed (Delta Q/Delta t) is used. The approximation method counts impulses for a fixed period of time. This turns out to not be very accurate. If the fixed time expires between position marks, the exact motor speed can not be determined. In our system, we use speed feedback to control the motor. When the fixed time expires, the speed feedback module continues counting until the next position mark sends a purse. This enables the speed feedback module to accurately determine the amount of time required to reach the new position. Once the new position is reached and the new time is determined, the actual speed of the motor can be calculated. The speed feedback system was designed in VHDL and implemented with an Altera EPLD. The design consists of common components including counters and registers. The core of the design is a small divider to do the speed calculation. We determined that the best tradeoff of speed and area was to use a radix two subtractive, non-restoring divider. The design has been implemented compactly on an Altera 10K20 chip and will be integrated into a motor control system. One of the challenges was to integrate the FPGA implementation with a system that operates over a large range of motor speeds, from much slower than the operating speed of the FPGA, to comparable to the operating speed. At slow motor speeds the FPGA implementation needs to generate a steady output to the motor.

关键词： reconfigurable computing fpgas adaptive motor control binary division

来源：评论

学校读者我要写书评

暂无评论

Sassy: A language and optimizing compiler for image processing on reconfigurable computing systems 1st

引用

1st International conference on Computer Vision Systems, ICVS 1999

作者： Hammes, Jeffrey P. Draper, Bruce A. BÖHm, A P Willem Colorado State University Fort CollinsCO80523 United States

ISBN: (纸本)3540654593

This paper presents Sassy, a single-assignment variant of the C programming language developed in concert with Khoral Inc. and designed to exploit both coarse-grain and fine-grain parallelism in image processing applications. Sassy programs are written in the Khoros software development environment, and can be manipulated inside Cantata (the Khoros GUI). The Sassy language supports image processing with true multidimensional arrays, sophisticated array access and windowing mechanisms, and built-in reduction operators (e.g. histogram). At the same time, Sassy restricts C so as to enable compiler optimizations for parallel execution environments, with the goal of reducing data traffic, code size and execution time. In particular, the Sassy language and its optimizing compiler target reconfigurable systems, which are fine-grain parallel processors. reconfigurable systems consist of field-programmable gate arrays (fpgas), memories and interconnection hardware, and can be used as inexpensive co-processors with conventional workstations or PCs. The compiler optimizations needed to generate highly optimal host, FPGA, and communication code, are discussed. The massive parallelism and high throughput of reconfigurable systems makes them well-suited to image processing tasks, but they have not previously been used in this context because they are typically programmed in hardware description languages such as VHDL. Sassy was developed as part of the Cameron project, with the goal of elevating the programming level for reconfigurable systems from hardware circuits to programming language. © Springer-Verlag Berlin Heidelberg 1999.

关键词： Image processing

来源：评论

学校读者我要写书评

暂无评论

Using the KressArray for reconfigurable computing

Using the KressArray for reconfigurable computing

引用

conference on Configurable computing - technology and applications

作者： Hartenstein, R Herz, M Hoffmann, T Nageldinger, U Univ Kaiserslautern D-67663 Kaiserslautern Germany

ISBN: (纸本)0819429872

Multimedia applications commonly require high computation power mostly in conjunction with high data throughput. As an additional challenge, such applications are increasingly used in handheld devices, where also small package outlines and low power aspects are important. Many research approaches have shown, that accelerators based on reconfigurable hardware can satisfy those performance demands. Most of these approaches use commercial fine-grained fpgas to implement reconfigurable accelerators. However, it has shown, that these devices are not always well suited for reconfigurable computing. The drawbacks here are the area-inefficiency and the insufficiency of the available design-tools. Besides the fine-grained fpgas, coarse-grained reconfigurable architectures have been developed, which are more area efficient and better suited for computational purposes. In this paper, an implementation of such an architecture, the KressArray, is introduced and its use in the Map-oriented Machine with Parallel Data Access (MoM-PDA) is shown. The MoM-PDA is an FPGA-based custom computing machine, which is able to perform concurrent memory accesses by means of a dedicated memory organization scheme. The benefits of this architecture are illustrated by an application example.

关键词： reconfigurable computing parallel data access coarse grained reconfigurable architectures KressArray accelerators Xputer image processing

来源：评论

学校读者我要写书评

暂无评论

Design and implementation of a high level image processing machine using reconfigurable hardware

Design and implementation of a high level image processing m...

引用

conference on Configurable computing - technology and applications

作者： Donachy, P Crookes, D Bouridane, A Alotaibi, K Benkrid, A British Telecom Belfast Engn Ctr Belfast BT1 6FD Antrim North Ireland

ISBN: (纸本)0819429872

Image Processing requires high computational power, plus the ability to experiment with algorithms. Recently, reconfigurable hardware devices in the form of Field Programmable Gate Arrays (fpgas) have been proposed as a way of obtaining high performance at an economical price. At present, however, users must program fpgas at a very low level and have a detailed knowledge of the architecture of the device being used. To try to improve design time for FPGA-based image processing, this paper reports on the design and realisation of an FPGA-based image processing machine and its associated high level programming model. Central to the design of architecture blocks is the 'design to fit' approach. The abstract machine is based on a PC host system with a PCI-bus add-on card containing Xilinx XC6200 series FPGA(s). The machine's high level instruction set is based on the operators of Image Algebra. XC6200 series FPGA configurations have been developed to implement each high level instruction.

关键词： image processing image algebra FPGA abstract machine architectures design to fit

来源：评论

学校读者我要写书评

暂无评论

Implementation of Adaptive Logic Networks on an FPGA board

Implementation of Adaptive Logic Networks on an FPGA board

引用

conference on Configurable computing - technology and applications

作者： Oliver, JP de Oliveira, AF Acle, JP de la Vega, RJ Canetti, R Univ Republ Fac Ingn Inst Ingn Elect Montevideo Uruguay

ISBN: (纸本)0819429872

This work is part of a project that studies the implementation of neural network algorithms in reconfigurable hardware as a way to obtain a high performance neural processor. The results for Adaptive Logic Network (ALN) type binary networks with and without learning in hardware are presented. The designs were made on a hardware platform consisting of a PC compatible as the host computer and an ALTERA RIPP10 reconfigurable board with nine FLEX8K fpgas and 512KB RAM. The different designs were run on the same hardware platform, taking advantage of its configurability. A software tool was developed to automatically convert the ALN network description resulting from the training process with the ATREE 2.7 for Windows software package into a hardware description file. This approach enables the easy generation of the hardware necessary to evaluate the very large combinatorial functions that results in an ALN. In an on-board learning version, an ALN basic node was designed optimizing it in the amount of cells per node used. Several nodes connected in a binary tree structure for each output bit, together with a control black, form the ALN network. The total amount of logic available on-board in the used platform limits the maximum size of the networks from a small to medium range. The performance was studied in pattern recognition applications. The results are compared with the software simulation of ALN networks.

关键词： fpgas reconfigurable hardware artificial neural networks Adaptive Logical Networks (ALN)

来源：评论

学校读者我要写书评

暂无评论

A flexible multiservice ATM network interface using reconfigurable logic devices

A flexible multiservice ATM network interface using reconfig...

引用

conference on Configurable computing - technology and applications

作者： Weber, B Ouvradou, G Rolin, P Ecole Natl Super Telecommun F-29285 Brest France

ISBN: (纸本)0819429872

The ATM network was designed to deal with all sorts of traffic such as data-, voice-, and video-traffic. This is achieved using service categories (CBR, VER, ABR, and UBR) and AAL protocols. Existing ATM Network Interface Cards (NICs) realize the full-range of service categories but generally perform only one AAL protocol (AAL1 <-> AAL5). Research in our laboratory investigates possibilities that offer reconfigurable logic (FPGA) in the field of ATM NICs. In this paper, we present a flexible multiservice ATM network interface. It is flexible through the use of FPGA (and eventually other resources like multipurpose processors) and it is multiservice as it enables lots of possible AAL-protocols, including complete AAL1 and AAL5, at one and the same time and also new specialized, proprietary adaptation protocols. These new protocols could be specially designed for security, compression, data structure recognition,... Here present bandwidth estimations based on sample implementations and possible target architectures using different types of fpgas (statically or partially/dynamically reconfigurable). Their advantages and drawbacks are discussed. Finally we try to isolate the open questions related to the flexible multiservice network interface.

关键词： ATM AAL reconfigurable logic FPGA and NIC

来源：评论

学校读者我要写书评

暂无评论

A novel single chip evolutionary hardware design using fpgas

A novel single chip evolutionary hardware design using FPGAs

引用

conference on Configurable computing - technology and applications

作者： Slorach, CG Sharman, KC Univ Glasgow Dept Elect & Elect Engn Glasgow G12 8LT Lanark Scotland

ISBN: (纸本)0819429872

There has recently been much research interest in the concept of evolvable hardware - partly due to the rapid technological changes brought about by reconfigurable devices and partly due to the success of evolutionary techniques. in software systems. In this paper we contribute to this effort and present a scalable single chip solution for evolvable hardware. This employs standard off-the-shelf Field Programmable Gate Arrays (fpgas) as opposed to a custom silicon solution. The resulting system permits the automatic evolution of digital circuits to match some given specification and has significant advantages and features over existing design flows. The system employs evolutionary programming (EP) as the adaptive design process - however the underlying system architecture is independent of the evolutionary algorithm being employed and so may be changed as required. The system is described in the hardware description language VHDL and hence is portable to other programmable devices satisfying the architectural requirements which are also detailed.

关键词： evolutionary algorithms evolutionary electronics evolutionary programming (EP) evolvable hardware (EHW) adaptive systems field programmable gate arrays (fpgas) self-morphing circuitry single chip evolvable hardware

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共42页 << < 33 34 35 36 37 38 39 40 41 42 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：