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A novel single chip evolutionary hardware design using fpgas

A novel single chip evolutionary hardware design using FPGAs

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conference on Configurable computing - technology and applications

作者： Slorach, CG Sharman, KC Univ Glasgow Dept Elect & Elect Engn Glasgow G12 8LT Lanark Scotland

ISBN: (纸本)0819429872

There has recently been much research interest in the concept of evolvable hardware - partly due to the rapid technological changes brought about by reconfigurable devices and partly due to the success of evolutionary techniques. in software systems. In this paper we contribute to this effort and present a scalable single chip solution for evolvable hardware. This employs standard off-the-shelf Field Programmable Gate Arrays (fpgas) as opposed to a custom silicon solution. The resulting system permits the automatic evolution of digital circuits to match some given specification and has significant advantages and features over existing design flows. The system employs evolutionary programming (EP) as the adaptive design process - however the underlying system architecture is independent of the evolutionary algorithm being employed and so may be changed as required. The system is described in the hardware description language VHDL and hence is portable to other programmable devices satisfying the architectural requirements which are also detailed.

关键词： evolutionary algorithms evolutionary electronics evolutionary programming (EP) evolvable hardware (EHW) adaptive systems field programmable gate arrays (fpgas) self-morphing circuitry single chip evolvable hardware

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Comparing computing machines

Comparing computing machines

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conference on Configurable computing - technology and applications

作者： DeHon, A Univ Calif Berkeley Berkeley CA 94720 USA

ISBN: (纸本)0819429872

reconfigurable computing devices are emerging as a viable alternative to fixed-function components and programmable processors. To expand our knowledge of the role and optimization of these devices, it is increasingly imperative for us to compare implementations of tasks and subroutines across this wide spectrum of implementation options. The fact Chat most processors, fpgas, ASICs, and memories are fabricated in a uniform technology medium, CMOS VLSI, where area scaling is moderately well understood eases our comparison task. Nonetheless, the rapid pace of technology, limited device size selection, and economic artifacts complicate the picture. In this paper, we look at the task of comparing computing machines, reviewing normalization techniques and many important issues which arise during comparisons. This paper includes examples intended to underscore the methodology and comparison issues, but does not attempt to make definitive conclusions about the merits of the technology alternatives from the small sample set. The immediate intent of this work is to help designers faced with tradeoffs between technological alternatives. The longer term intent is to help the community collect and analyze the broad-based data. needed to Better understand the range of available computing options.

关键词： configurable computing FPGA programmable architectures performance comparison computational density

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Parallel synthesis of large combinational circuits for fpgas

Parallel synthesis of large combinational circuits for FPGAs

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High Performance computing and Networking Europe 1997 conference

作者： Lemarchand, L Univ Bretagne Occidentale LIBr Brest BELARUS

ISBN: (纸本)3540628983

reconfigurable circuits such as fpgas become much larger, reaching the 100.000 gates, and are a credible alternative for some computation intensive applications. However, to the accepted, very important progresses must be achieved in the programming methods, since several bottlenecks limit the design process for FPGA. Generating a circuit from an high level specification involves numerous tasks. The goal of the logic synthesis task is to improve the circuit on criteria such as speed or area, and to take technology constraints into account. The aim of our work is to speed up this phase, since it involves important runtime and huge memory requrments, even if heuristics are used.

关键词： Combinational circuits Field programmable gate arrays design process Traffic Bottlenecks Heuristics Logic synthesis Parallel Lines synthesis

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7th International Workshop on Field-Programmable Logic and applications, FPL 1997

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7th International Workshop on Field Programmable Logic and applications, FPL 1997

ISBN: (纸本)3540634657

The proceedings contain 51 papers. The special focus in this conference is on Devices and Architectures. The topics include: Multicontext dynamic reconfiguration and real time probing on a novel mixed signal programmable device with on-chip microprocessor;CAD-oriented FPGA and dedicated CAD system for telecommunications;a three dimensional FPGA architecture, its fabrication, and design tools;extending dynamic circuit switching to meet the challenges of new FPGA architectures;performance evaluation of a full speed PCI initiator and target subsystem using fpgas;implementation of pipelined multipliers on xilinx fpgas;the XC6200DS development system;thermal monitoring on fpgas using ring-oscillators;a reconfigurable approach to low cost media processing;a flexible platform for codesign and dynamic reconfigurable computing research;stream synthesis for a wormhole run-time reconfigurable platform;pipeline morphing and virtual pipelines;parallel graph colouring using fpgas;run-time compaction of FPGA designs;partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement;a case study of partially evaluated hardware circuits;run-time parameterised circuits for the xilinx XC6200;automatic identification of swappable logic units in XC6200 circuitry;towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic;exploiting reconfigurability through domain-specific systems;technology mapping by binate covering;a new packing, placement and routing tool for FPGA research;technology mapping of heterogeneous LUT-based fpgas and technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based fpgas.

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A high performance data and video recorder with real-time lossless compression

A high performance data and video recorder with real-time lo...

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conference on Multimedia Hardware Architectures 1997

作者： Beckstead, JA Aceto, S Conerty, M Nordhauser, S InterScience Inc. 105 Jordan Rd. Troy 12180 NY United States

ISBN: (纸本)0819424323

Over the last decade, the video camera has become a common diagnostic/tool for many scientific, industrial and medical applications. The amount of data collected by video capture systems can be enormous. For example, standard NTSC video requires 5 MBytes/sec, with many groups wanting higher resolution either in bit-depth, spatial resolution and/or frame speed. Despite great advances in video capture systems developed for the mass media and teleconferencing markets, the smaller markets of scientific and industrial applications have been ignored. This is primarily due to their need to maintain the independent nature of each camera system and to maintain the high quality of the video data. Many of the commercial systems are capable of digitizing a single camera (B/W or color) or multiple synchronized B/W cameras using an RGB color video capture chip set. In addition,most manufacturers utilize lossy compression to reduce the bandwidth before storing the data to disk To address the needs of the scientific community, a high-performance data and video recorder has been developed. This system utilizes field programmable gate arrays (fpgas) to control the analog and digital signals and to perform realtime lossless compression on the incoming data streams. Due to the flexibility inherent in the system, it is able to be configured for a variety of camera resolutions, frame rates and compression algorithms. In addition, alternative general purpose data acquisition modules are also being incorporated into the design. The modular design of the video/data recorder allows the carrier components to be easily adapted to new bus technology as it becomes available or the data acquisition components to be tailored to a specific application. Details of the recorder architecture will be presented along with examples A lossless compression ratio of 3:1 has been obtained on fusion plasma expected, allowing the video recorder to capture up to ten independent video inputs and apply the compre

关键词： lossless compression video storage Field Programmable Gate Arrays real-time video archiving reconfigurable computing

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5th International Workshop on Field-Programmable Logic and applications, FPL 1995

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5th International Workshop on Field-Programmable Logic and applications, FPL 1995

ISBN: (纸本)3540602941

The proceedings contain 46 papers. The special focus in this conference is on Architectures;Platforms;Tools;Arithmetic and Signal Processing. The topics include: The Design of a New FPGA Architecture;Migraton of a Dual Granularity Globally Interconnected PLD Architecture to a 0.5 µm TLM Process;Self-Timed FPGA Systems;XC6200 Fastmap ™ Processor Interface;The Teramac Configurable Computer Engine;Telecommunication-Oriented FPGA and Dedicated CAD System;A Configurable Logic Processor for Machine Vision;Extending DSP-Boards wih FPGA-Based Structures of Interconnection;High-Speed Region Detection and Labeling Using an FPGA Based Custom computing Platform;Using fpgas as Control Support in MIMD Executions;Customised Hardware Based on the REDOC iiI Algorithm for High-Performance Date Ciphering;Using reconfigurable Hardware to Speed up Product Development and Performance;Creation of Hardware Objects in a reconfigurable Computer;Rapid Hardware Prototyping of Digital Signal Processing Systems Using fpgas;Delay Minimal Mapping of RTL Structures onto LUT Based fpgas;Some Notes Qn Power Management on FPGA-Based Systems;An Automatic Technique for Realising User Interaction Processing in PLD Based Systems;The Proper Use of Hierarchy in HDL-Based High Density FPGA Design;Compiling Regular Arrays onto fpgas;Compiling Ruby into fpgas;The CSYN Verilog Compiler and Other Tools;A VHDL Design Methodolgy for fpgas;VHDL-Based Rapid Hardware Prototyping Using FPGA technology;Integer Programming for Partitioning in Software Oriented Codesign;Test Standard Serves Dual Role as On-Board Programming Solution;Advanced Method for Industry Related Education with an FPGA Design Self-Learning Kit.

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An analysis of FPGA-based custom computers for DSP applications

An analysis of FPGA-based custom computers for DSP applicati...

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Proceedings of the 1994 IEEE International conference on Acoustics, Speech and Signal Processing. Part 2 (of 6)

作者： Bergmann, Neil W. Mudge, J. Craig CSIRO/Flinders Joint Research Centre in Information Technology Flinders University GPO Box 2100 AdelaideSA Australia

Field programmable gate arrays (fpgas) can be rapidly reconfigured to provide different digital logic functions. When such FPGA logic circuits are incorporated within a stored-program computer, the result is a machine where the programmer can design both the software and the hardware that will execute that software. This paper first surveys this area of custom computing. It then describes a new custom computing architecture which uses a processing node with three sections: a standard arithmetic chip, static RAM and reconfigurable logic for operand handling. Finally an analysis of the suitability of this new approach for implementation of DSP applications shows it to be worthy of further investigation. © 1994 IEEE.

关键词： Field programmable gate arrays (FPGA)

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4th International Workshop on Field-Programmable Logic and applications, FPL 1994

4th International Workshop on Field-Programmable Logic and A...

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4th International Workshop on Field-Programmable Logic and applications, FPL 1994

ISBN: (纸本)9783540584193

The proceedings contain 63 papers. The special focus in this conference is on Field-Programmable Logic and applications. The topics include: A test methodology applied to cellular logic programmable gate arrays;influence of logic block layout architecture on FPGA performance;a global routing heuristic for fpgas based on mean field annealing;power dissipation driven FPGA place and route under delay constraints;FPGA technology mapping for power minimization;specification and synthesis of complex arithmetic operators for fpgas;a speed-up technique for synchronous circuits realized as LUT-based fpgas;an efficient technique for mapping RTL structures onto fpgas;a testbench design method suitable for FPGA -based prototyping of reactive systems;using consensusless covers for fast operating on Boolean functions;formal verification of timing rules in design specifications;a high-speed rotation processor;a reprogrammable processor for fractal image compression;implementing GCD systolic arrays on FPGA;formal cad techniques for safety-critical FPGA design and deployment in embedded subsystems;FPGA based reconfigurable architecture for a compact vision system;a new FPGA architecture for word-oriented datapaths;image processing on a custom computing platform;a superscalar and reconfigurable processor;a fast FPGA implementation of a general purpose neuron;data-procedural languages for FPL-based machines;implementing on line arithmetic on PAM;constraint-based hierarchical placement of parallel programs;simulating static and dynamic faults in BIST structures with a FPGA based emulator;meaningful benchmarks for logic optimization of table-lookup fpgas and educational use of field programmable gate arrays.

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An analysis of FPGA-based custom computers for DSP applications

An analysis of FPGA-based custom computers for DSP applicati...

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International conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： N.W. Bergmann J.C. Mudge CSIRO Flinders Joint Research Centre in Information Technology Flinders University Adelaide SA Australia

关键词： Computer applications Digital signal processing Application software Field programmable gate arrays Programmable logic arrays Logic functions Logic circuits Programming profession Software design Hardware

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