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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

共 419 条记录，以下是41-50 订阅

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On the Feasibility of TERO-Based True Random Number Generator on Xilinx fpgas

On the Feasibility of TERO-Based True Random Number Generato...

引用

International conference on Field Programmable Logic and applications

作者： Naoki Fujieda Department of Electrical and Electronics Engineering Aichi Institute of Technology Toyota Aichi Japan

The following topics are dealt with: field programmable gate arrays; logic design; parallel processing; microprocessor chips; reconfigurable architectures; cloud computing; neural nets; power aware computing; parallel...

ISBN: (数字)9781728199023

ISBN: (纸本)9781728199030

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Design of a Flexible Schönhage-Strassen FFT Polynomial Multiplier with High- Level Synthesis to Accelerate HE in the Cloud

Design of a Flexible Schönhage-Strassen FFT Polynomial Mult...

引用

2019 International conference on reconfigurable computing and fpgas, ReConFig 2019

作者： Millar, Kevin Lukowiak, Marcin Radziszowski, Stanislaw Rochester Institute of Technology Department of Computer Engineering United States

ISBN: (纸本)9781728119571

Homomorphic Encryption (HE) allows for encrypted data to be sent to, stored, and operated on by untrusted parties without the risk of privacy compromise. The benefits and applications of HE are far reaching, especially in regard to cloud computing. However, current HE solutions require a large number of resource intensive arithmetic operations such as high precision, high degree polynomial multiplication. This work aims to accelerate the multi-precision arithmetic operations used in HE with specific focus on an implementation of the Schönhage-Strassen Fast Fourier Transform (FFT)-based multiplication algorithm. It is planned to be incorporated into a larger HE library of arithmetic functions tuned for High-Level Synthesis (HLS) that enables flexible solutions for hardware/software systems on reconfigurable cloud resources. The developed FFT based polynomial multiplier exhibits flexibility in the selection of HE security parameters facilitating its use in a wide range of schemes and applications. The design yields substantial speedup over the polynomial multiplication functions implemented in the Number Theory Library (NTL) utilized by software based HE solutions. © 2019 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Efficient OS Hardware Accelerators Preemption Management in FPGA 18

Efficient OS Hardware Accelerators Preemption Management in ...

引用

International conference on Field-Programmable technology (ICFPT)

作者： Tian, Ye Prevotet, Jean-Christophe Nouvel, Fabienne Univ Europe Bretagne Bretagne France INSA IETR UMR 6164 F-35708 Rennes France

ISBN: (纸本)9781728129433

The management of reconfiguration in fpgas constitutes a hot topic in a lot of domains. In such devices, a reconfigurable fabric is generally combined with a processor to guarantee high computing performance with a limited amount of hardware resources. Most of these devices generally feature an operating system (OS) that interacts with hardware Intellectual Property (IP) resources. Software tasks (managed by the OS) may then access hardware resources concurrently and dedicated mechanisms have to be provided to manage resource sharing efficiently. The problem is even bigger if hardware resources are localized in a reconfigurable area. In this paper, we deal with the problem of sharing hardware resources in a reconfigurable device. We propose a preemption mechanism for hardware resources that may reduce the reconfiguration time overhead to be compatible with the timing constraints of most embedded applications.

关键词： Embedded Systems Micro-Kernel reconfigurable Architectures Hardware Preemption

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Possibilities and Challenges for reconfigurable Hardware and Cloud Architectures in Data-Intensive Scientific applications

Possibilities and Challenges for Reconfigurable Hardware and...

引用

International conference on Software Defined Systems (SDS)

作者： Mohammed Bawatna Oliver Knodel Rainer G. Spallek Institut für Technische Informatik Technische Universität Dresden Dresden Germany Department of Computational Science Helmholtz Zentrum Dresden Rossendorf Dresden Germany

ISBN: (数字)9781728172194

ISBN: (纸本)9781728172200

Advances in process technology and new design tools have expanded the scope of embedded systems. This ranges from the implementation in several chips on board to module groups in integrated circuits. reconfigurable hardware and, in particular, fpgas are used more frequently in scientific applications, where they enable the development of complex and intelligent field devices. Furthermore, this increased the use of a platform-based design approach that facilitates the development and verification of complex fpgas through the full reuse of hardware and software modules. Especially in the area of heterogeneous accelerators, which can improve the exploitation of modern data centers. Another critical aspect in the evolution of embedded systems is the trend towards networking embedded nodes using specialized computational and networking technologies called cloud computing. In this paper, we will present our data-intensive experiments at the terahertz source at ELBE accelerator-based light source, and its integration into a reproducible data management workflow at the heterogeneous cluster in our data centre.

关键词： Field programmable gate arrays Cloud computing Hardware Data centers Embedded systems Computer architecture

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An Intelligent Algorithm for Mapping of applications on Parallel reconfigurable Systems

An Intelligent Algorithm for Mapping of Applications on Para...

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International conference of Signal Processing and Intelligent Systems (ICSPIS)

作者： Masoud Yazdani Rad Shakiba Shahbandegan School of Electrical Engineering Iran University of Science and Technology Tehran Iran

ISBN: (数字)9781728186290

ISBN: (纸本)9781728186306

An increasing demand for computational power in daily used applications has led to implementation of different computing platforms. Among them, reconfigurable platforms which are based on fpgas, have been widely used in recent years. While they are flexible, the communication cost between different computational tasks implemented in different locations of FPGA is one of the main challenges when it comes to improving the performance. In this paper, mapping of application tasks into processing platforms is studied. We presented a new method based on neural networks. Firstly, using Node2vec embedding algorithm, dimensions reduction, and rotation and scale, an initial mapping of task interaction graph nodes into processing structure fpgas was obtained. Secondly, the dilation and maximum capacity utilization optimization were done using the stochastic gradient descent (SGD) method and loss functions. After performing experiments and comparing the proposed method with a similar method, results showed that the proposed method was superior in performance in terms of dilation (11.28%) and showed a poorer performance in terms of maximum capacity utilization (4.30%).

关键词： Dimensionality reduction Scalability Signal processing algorithms Signal processing Task analysis Time complexity Field programmable gate arrays

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A New reconfigurable Architecture with applications to IoT and Mobile computing 1st

A New Reconfigurable Architecture with Applications to IoT a...

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1st IFIP International Cross-Domain conference on Internet of Things, IFIPIoT 2018, held at the 24th IFIP World Computer Congress, WCC 2018

作者： Gharehbaghi, Amir Masoud Maruoka, Tomohiro Fujita, Masahiro The University of Tokyo Tokyo Japan

ISBN: (纸本)9783030156503

Traditional reconfigurable devices known as fpgas utilize a complicated programmable routing network to provide flexibility in connecting different logic elements across the FPGA chip. As such, the routing procedure may become very complicated, especially in the presence of tight timing constraints. Moreover, the routing network itself occupies a large portion of chip area as well as consumes a lot of power. Therefore, limiting their usage in mobile applications or IoT devices with higher performance and lower energy demands. In this paper, we introduce a new reconfigurable architecture which only allows communication between neighboring logic elements. This way, the routing structure and the routing resources become much simpler than traditional fpgas. Moreover, we present two different method for scheduling and routing in our new proposed architecture. The first method deals with general circuits or irregular computations and is based on integer linear programming. The second method is for regular computations such as convolutional neural networks or matrix operations. We have shown the mapping results on ISCAS benchmark circuits as general irregular computations as well as heuristics to improve the efficiency of mapping for larger benchmarks. Moreover, we have shown results on regular computations including matrix multiplication and convolution operations of neural networks. © 2019, The Author(s).

关键词： Mapping

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A Field Programmable Process-In-Memory Architecture Based on RRAM technology

A Field Programmable Process-In-Memory Architecture Based on...

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International conference on Mechanical, Control and Computer Engineering (ICMCCE)

作者： Yuan Liang Longxiang Yin Ning Xu School of Computer Science and Technology Wuhan University of Technology Wuhan China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China School of Information Engineering Wuhan University of Technology Wuhan China

Conventional reconfigurable architectures, e.g., Field-Programmable Gate Array (FPGA), are confronted with the inflexibility of the on-chip local memory architecture and the scarce memory resource, which result in the inflexibility to deal with the current memory-thirsty data-intensive applications. Emerging nonvolatile devices, such as resistive random-access memory (RRAM), can operate in a logic-in-memory way, i.e., they can act as both a nonvolatile memory element and a switch, and thus, have the potential to provide higher flexibility and data processing ability. We propose a field-programmable logic-in-memory architecture based on RRAM technology, which is a two-dimensional tile array, where each tile is an RRAM-based crossbar array and can be remolded into three basic modes including logic, interconnect and memory. We further develop a specific adaptive algorithm for placement and routing, which can well exploit the logic-in-memory architecture characteristics. Comparing with traditional fpgas, our architecture shows 1.9x lower power consumption, 2.8x lower delay, and 5.6x higher performance.

关键词： Nonvolatile memory Computer architecture Switches Routing Delays System-on-chip reconfigurable architectures

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Performance and energy efficiency analysis of reverse time migration on a FPGA platform 5

Performance and energy efficiency analysis of reverse time m...

引用

5th IEEE/ACM International Workshop on Heterogeneous High-Performance reconfigurable computing, H2RC 2019

作者： Bittencourt, Joao Carlos Souza, Joao Marcelo Furtado, Adhvan Nascimento, Erick Giovani Sperandio Oliveira, Wagner Luiz Nascimento, Anderson Fialho, Leonardo Oliveira, Joaquim Ranyere Tutu, Rodrigo Rojas, Georgina Jesus, Laue Rami Lima, Andre Center of Technology and Exact Sciences Federal University of Reconcavo da Bahia Cruz das Almas Brazil Super Computing Center SENAI/CIMATEC Salvador Brazil Politechnical Institute Federal University of Bahia Salvador Brazil

ISBN: (纸本)9781728159997

Reverse time migration (RTM) modeling is a computationally intensive component in the seismic processing workflow of oil and gas exploration, often demanding the manipulation of terabytes of data. Therefore, the computational kernels of the RTM algorithms need to access a large range of memory locations. However, most of these accesses result in cache misses, degrading the overall system performance. GPGPUs and fpgas are the two endpoints in the spectrum of acceleration platforms, since both can achieve better performance in comparison to CPU on several high-performance applications. Recent literature highlights FPGA better energy efficiency when compared to GPGPU. The present work proposes a FPGA accelerated platform prototype targeting the computation of the RTM algorithm on an HPC environment. Experimental results highlight that speedups of 112x can be achieved, when compared to a sequential execution on CPU. When compared to a GPU, the power consumption has been reduced up to 55%. © 2019 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Dimension Reduction for Efficient Pattern Recognition in High Spatial Resolution Data Using Quantum Algorithms 32

Dimension Reduction for Efficient Pattern Recognition in Hig...

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32nd IEEE International System-on-Chip conference (IEEE SOCC)

作者： Mahmud, Naveed El-Araby, Esam Univ Kansas Elect Engn & Comp Sci Lawrence KS 66045 USA

ISBN: (纸本)9781728134826

With the promising advancement in quantum computing technology in the last decade, there is a strong motivation to find suitable applications for quantum algorithms and quantum computers. Domains such as High Energy Physics (iiEP) have an enormous readout count of high-resolution data. Performing pattern recognition on this readout is computationally. , challenging and time-consuming because of the multi-dimensionality of the data. In this paper, we propose a methodology that employs quantum algorithms such as Quantum Wavelet Transform and Grover's search algorithm for time-efficient pattern recognition in data sets that are characterized by high spatial resolution and high dimensionality. The motivation behind using quantum algorithms is the potential speedup relative to classical methods, when performed by a quantum computer. In our proposed methodology, Quantum Wavelet Transform is performed on the high spatial resolution data to reduce its dimensionality while quantum Grover's search algorithm is employed to search for target patterns in the reduced data set. Performing the search operation on data with reduced spatial resolution, minimizes processing overheads and computation times. Moreover, use of quantum techniques yield faster results, compared to classical dimension reduction and search methods. We demonstrate the feasibility of the proposed methodology by emulating the quantum algorithms on classical hardware based on field programmable gate arrays (fpgas). A high performance reconfigurable computer (iiPRC) was used for the experimental evaluation. The obtained results are favorable towards our proposed approach.

关键词： Quantum computing Quantum Emulation

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Design of a Flexible Schönhage-Strassen FFT Polynomial Multiplier with High- Level Synthesis to Accelerate HE in the Cloud

Design of a Flexible Schönhage-Strassen FFT Polynomial Mult...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Kevin Millar Marcin Łukowiak Stanisław Radziszowski Rochester Institute of Technology

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