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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

共 419 条记录，以下是51-60 订阅

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A Runtime Power-Aware Phase Predictor for CGRAs

A Runtime Power-Aware Phase Predictor for CGRAs

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Guilherme Korol Michael Jordan Raul Silveira Silva Monica Magalhães Pereira Marcelo Brandalero Mateus Beck Rutzig Antonio Carlos Schneider Beck Institute of Informatics-Universidade Federal do Rio Grande do Sul (UFRGS) Porto Alegre Brazil Universidade Federal do Rio Grande do Norte (UFRN) Natal Brazil Chair of Computer Engineering-Brandenburg University of Technology (B-TU) Cottbus Germany Universidade Federal de Santa Maria (UFSM) Santa Maria Brazil

As computation migrates to the edge, energy efficiency is becoming even more critical in the design of electronic devices. Therefore, new applications for the Internet of Things pose a challenge for designers to find the optimal balance between performance and energy consumption. While Coarse Grained reconfigurable Architectures (CGRA) have been an alternative to provide the required acceleration, they are far from being the most energy-efficient, since their functional units may be underutilized by some applications. In this work, we introduce a novel approach to handle these CGRA resources, which leverages the variable usage of functional units due to the application program phases. By using our new approach and performing power-gating of under-utilized parts of the CGRA, we demonstrate that it is possible to achieve reductions of up to 52.3% in power dissipation and 75% in energy consumption.

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MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs

MBSS: A General Paradigm for Static Schedule for Nested Loop...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Xie, Shuai Zhao, Zhongyuan Sheng, Weiguang Wang, Qin Mao, Zhigang Shanghai Jiao Tong Univ Dept Micro NaNo Elect Shanghai Peoples R China

ISBN: (纸本)9781728119687

Coarse-grained reconfigurable Architectures (CGRAs) have been identified as a desirable platform for repetitive, datapath-oriented and computationally intensive applications. However, because the performance improvements are mostly achieved by exploiting the parallelism of the innermost loop, CGRAs are still poor at handling complicated applications, like loops with uncertain/unfixed boundary and imperfect nests. Existing compilation schemes for loops with dynamic loop boundary (DBLs) are inefficient and cannot support all types of control flow with no performance degradation under existing CGRAs architecture. This paper addresses the problems and makes the following contributions: i) To solve the issue of a loop with dynamic boundary, we present an improved architecture in hardware. The hybrid interconnects network is provided judiciously to support low latency control signal transformation and provide flexible power for complicated applications. ii) A precise problem formulation for DBL mapping onto CGRA. We abstract the problem with the generation of control and data flow graph (CDFG) and the mapping from CDFG to CGRA. iii) Based on the formulated problem, we provide Dynamic Boundary Static Schedule (DBSS) and Mixed Boundary Static Schedule (MBSS) methods to efficiently map the single level DBL and nested loop mixed with static and dynamic loop boundary separately. An evaluation is drafted finally under the enhanced hardware which is accessible to process the data flow with its high quality as well as the handcraft. MBSS takes performance improvement of 38%, 2:2x speed up on average and less energy consumption.

关键词： Coarse-grained reconfigurable Architectures DBL DBSS MBSS

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LeFlow: Automatic Compilation of TensorFlow Machine Learning applications to fpgas 17

LeFlow: Automatic Compilation of TensorFlow Machine Learning...

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17th International conference on Field-Programmable technology (FPT)

作者： Noronha, Daniel Holanda Gibson, Kahlan Salehpour, Bahar Wilton, Steven J. E. Univ British Columbia Dept Elect & Comp Engn Vancouver BC Canada

ISBN: (纸本)9781728102139

Acceleration of Machine Learning applications on Field-Programmable Gate Arrays (fpgas) has shown to have advantages over other computing platforms in recent work. However, since machine learning code is often specified in a high-level software language such as Python, the manual translation of the algorithm to either C code for high-level synthesis or to Register Transfer Level (RTL) code for synthesis is time consuming and requires the designer to have expertise in designing hardware. In order to show how we can make fpgas more accessible to software developers, we present a demonstration of LeFlow: an open-source tool which maps numerical computation models written in TensorFlow to synthesizable RTL. This demonstration includes two examples which begin with a model written in TensorFlow and show how a designer would use the LeFlow tool to generate Verilog, simulate the result, and synthesize the design to target fpgas.

关键词： Deep learning High level synthesis Machine learning reconfigurable architectures Software tools

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A Dynamically reconfigurable Platform for High-Performance and Low-Power On-Board Processing

A Dynamically Reconfigurable Platform for High-Performance a...

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NASA/ESA conference on Adaptive Hardware and Systems (AHS)

作者： Guerrieri, Andrea Kashani-Akhavan, Sahand Lombardi, Pasquale Belhadj, Bilel Ienne, Paolo Ecole Polytech Fed Lausanne Architecture Lab Lausanne Switzerland Syderal SA Gals Switzerland

ISBN: (纸本)9781538677537

fpgas (Field Programmable Gate Array) are an attractive technology for high-speed data processing in space missions due to their unbeatable flexibility and best performance-to-power ratio in comparison to software. However fpgas suffer from 3 major drawbacks: (1) higher programming effort is required with respect to software;(2) hardware resources need to be allocated for each implemented function in contrast to software functions which can be executed on the same processing hardware;and (3) fpgas are required to adopt radiation hardening techniques when deployed in a space environment. This paper presents a reconfigurable platform that demonstrates how modern fpgas can be considered as computing resources like any other, suitable for emerging spatial applications and not subjected to the above-mentioned drawbacks. In particular, we show that large fpgas can be split in different regions containing concurrently-running accelerators which can support the execution of a single or multiple applications. Then, in the same way as software-based multiprogrammed and multithreaded systems can dynamically create, schedule and execute threads, FPGA-based accelerators can be swapped in and out according to scheduling needs by exploiting their dynamic partial reconfiguration capability. A proof of concept cloud detection algorithm for Sentinel-2 multispectral images has been implemented and tested on our platform to validate the system's design principles and performance.

关键词： SoC FPGA COTS dynamic partial reconfiguration software thread hardware accelerator

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Performance Estimation for Exascale reconfigurable Dataflow Platforms 17

Performance Estimation for Exascale Reconfigurable Dataflow ...

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17th International conference on Field-Programmable technology (FPT)

作者： Yasudo, Ryota Coutinho, Jose G. F. Varbanescu, Ana L. Luk, Wayne Amano, Hideharu Becker, Tobias Keio Univ Tokyo Japan Imperial Coll London London England Univ Amsterdam Amsterdam Netherlands Maxeler Technol Ltd London England

ISBN: (纸本)9781728102139

The next generation high-performance computing platforms will need to support exascale computing. A promising path in achieving exascale is to embrace heterogeneity and specialised computing in the form of reconfigurable accelerators. However, assessing the feasibility of heterogeneous exascale systems requires fast and accurate performance prediction. This paper proposes PERKS, a novel performance estimation framework for reconfigurable dataflow platforms (RDPs). PERKS uses machine and application parameters to build an analytical model for predicting the performance of multi-accelerator systems. Moreover, model calibration is automatic, making the model flexible and usable for different machine configurations and applications. Our experimental results show that PERKS can predict the performance of current workloads and RDPs with an accuracy above 95%. We also demonstrate how the modelling scales to exascale workloads and exascale platforms.

关键词： exascale computing fpgas heterogeneous systems Performance modelling reconfigurable platforms

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Liquid Silicon-Monona: A reconfigurable Memory-Oriented computing Fabric with Scalable Multi-Context Support 18

Liquid Silicon-Monona: A Reconfigurable Memory-Oriented Comp...

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23rd International conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

作者： Zha, Yue Li, Jing Univ Wisconsin Dept Elect & Comp Engn Madison WI 53706 USA

ISBN: (纸本)9781450349116

With the recent trend of promoting Field-Programmable Gate Arrays (fpgas) to first-class citizens in accelerating compute-intensive applications in networking, cloud services and artificial intelligence, fpgas face two major challenges in sustaining competitive advantages in performance and energy efficiency for diverse cloud workloads: 1) limited configuration capability for supporting light-weight computations/on-chip data storage to accelerate emerging search-/data-intensive applications. 2) lack of architectural support to hide reconfiguration overhead for assisting virtualization in a cloud computing environment. In this paper, we propose a reconfigurable memory-oriented computing fabric, namely Liquid Silicon-Monona (L-Si), enabled by emerging nonvolatile memory technology i.e. RRAM, to address these two challenges. Specifically, L-Si addresses the first challenge by virtue of a new architecture comprising a 2D array of physically identical but functionally-configurable building blocks. It, for the first time, extends the configuration capabilities of existing fpgas from computation to the whole spectrum ranging from computation to data storage. It allows users to better customize hardware by flexibly partitioning hardware resources between computation and memory, greatly benefiting emerging search-and data-intensive applications. To address the second challenge, L-Si provides scalable multi-context architectural support to minimize reconfiguration overhead for assisting virtualization. In addition, we provide compiler support to facilitate the programming of applications written in high-level programming languages (e.g. OpenCL) and frameworks (e.g. TensorFlow, MapReduce) while fully exploiting the unique architectural capability of L-Si. Our evaluation results show L-Si achieves 99.6% area reduction, 1.43x throughput improvement and 94.0% power reduction on search-intensive benchmarks, as compared with the FPGA baseline. For neural network benchmarks, on aver

关键词： non-volatile memory processing-in-memory monolithic 3D stacking reconfigurable architecture multi-context architecture ternary content addressable memory binarized neural network

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Live Migration for OpenCL FPGA Accelerators 17

Live Migration for OpenCL FPGA Accelerators

引用

17th International conference on Field-Programmable technology (FPT)

作者： Vaishnav, Anuj Khoa Dang Pham Koch, Dirk Univ Manchester Sch Comp Sci Manchester Lancs England

ISBN: (纸本)9781728102139

fpgas are currently being deployed at a large scale across data-centres for various applications because of their performance and power benefits. In particular, cloud service operators are now offering fpgas as a Service. However, to completely integrate fpgas in a data-centre environment like standard software systems, support for fault tolerance and task migration is essential. In this paper, we propose a live migration technique for FPGA accelerators to provide support for fault tolerance, system maintenance, and resource management. Our technique allows migration of OpenCL accelerators not only within a single FPGA but also across fpgas with zero downtime. It achieves this by overlapping the computation with data-movements transparently from the user for OpenCL kernels. Moreover, distributed check-pointing mechanisms can be employed to recover from unknown faults with minimal loss of completed work. Altogether it enables system updates such as changing the static FPGA configuration or upgrading the OS without an interruption of service.

关键词： cloud computing data centres fault tolerance FPGA accelerators live migration opencl resource management system maintenance

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FPGA Performance Optimization Plan for High Power Conversion 1

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2nd International conference on Soft computing Systems (ICSCS)

作者： Muthukumar, P. Kanthan, Padma Suresh Lekshmi Immanuel, T. Baldwin Eswaramoorthy, K. PVP Siddhartha Inst Technol Dept Elect & Elect Engn Vijayawada 520007 India Baselios Mathew II Coll Engn Dept Elect & Elect Engn Sasthamkotta 690521 Kerala India AMET Deemed Univ Dept Elect & Elect Engn Chennai 603112 Tamil Nadu India Anna Univ Dept Elect & Elect Engn Chennai 600025 Tamil Nadu India

ISBN: (数字)9789811319365

ISBN: (纸本)9789811319365;9789811319358

One of the major part of any power converter system is a blistering implementation of PWM algorithm for high power conversion. It must fulfil both requirements of power converter hardware topology and computing power necessary for control algorithm implementation. The emergence of multi-million-gate fpgas with large on-chip RAMs and a processor cores sets a new trend in the design of fpgas which are exceedingly used to generate the PWM in the area of power electronics. Of late, more and more large complex designs are getting realized using fpgas, because of less NRE cost and shorter development time. The share of Programmable Logic Devices (PLD), especially fpgas, in the semiconductor logic market is tremendously growing year-on-year. This calls for an increased controllability of designs, in terms of meeting both area and timing performance, to really derive the perceived benefits. The recent strides in FPGA technology favour the realization of large high-speed designs, which were only possible in an ASIC, in FPGA now. However the routing delay being still unpredictable and the pronounced nature of routing delay over logic delay, in today's fpgas impedes the goal of early timing convergence. This paper introduces the few techniques for controlling the design area/ time right from architecture stage and the technique can adopt for any FPGA based design applications including the high power conversion. This paper also describes the trade off between Area, speed and power of the optimization techniques.

关键词： Field Programmable Gate Array Programmable Logic Devices Application specific integrated circuits Flip flops Optimization Register transfer logic Block ram Embedded array block Configurable logic blocks

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Discrete and Logico-numerical Control for Dynamic Partial reconfigurable FPGA-based Embedded Systems : a Case Study 2

Discrete and Logico-numerical Control for Dynamic Partial Re...

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2nd IEEE conference on Control technology and applications (CCTA)

作者： Gueye, Soguy Mak-Kare Delaval, Gwenael Rutten, Eric Diguet, Jean-Philippe Univ Grenoble Alpes CNRS Inria LIG F-38000 Grenoble France Univ Bretagne Sud CNRS LAB STICC F-56321 Lorient France

ISBN: (纸本)9781538676981

Embedded systems need to be more and more self-adaptive, in order to better manage their constrained resources, and to better take into account evolutions in their environment and in their computing architecture. They can benefit from Field Programmable Gate Array (FPGA) architectures, which supports Dynamic Partial Reconfiguration (DPR) of the running fonctions, enabling improved performance and power consumption. The reconfigurations need to be decided and controlled in a closed loop. We approach this problem by applying techniques from the area of Supervisory Control for Discrete Event Systems (DES), where the space of configurations at the different levels (application, tasks, hardware platform) are modeled with automata, using the tools Heptagon/BZR and ReaX. This paper contributes with (i) generic modeling of the behaviors and objectives;(ii) applications of Discrete Controller Synthesis (DCS), especially logico-numerical control;(iii) concrete implementation on a FPGA hardware platform for an embedded video processing case study.

关键词： Discrete Event Systems Application Hardware/Software Embedded Systems

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Towards a Type 0 Hypervisor for Dynamic reconfigurable Systems

Towards a Type 0 Hypervisor for Dynamic Reconfigurable Syste...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Janssen, Benedikt Korkmaz, Fatih Derya, Halil Huebner, Michael Ferreira, Mario Lopes Ferreira, Joao Canas Ruhr Univ Bochum Embedded Syst Informat Technol Bochum Germany Univ Porto INESC TEC Porto Portugal Univ Porto Fac Engn Porto Portugal

ISBN: (纸本)9781538637975

The usage of application-specific hardware based on Field-Programmable Gate Arrays (FPGA) has proven its benefits. Current system-on-chips, which contain FPGA fabric, supporting dynamic partial reconfiguration, enable a dynamic hardware acceleration for hardware/software co-designs. With the trend to consolidate multiple computing systems into a single system, applications with mixed criticalities can come into conflict. With our approach, we are exploring the possibility to utilize dedicated hardware for the system management and benefit from possible parallelization of applications and system management tasks.

关键词： FPGA Zynq Hypervisor Virtualitzation Microkernel Mixed-Critical Dynamic Partial Reconfiguration

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