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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

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IP Core of Coprocessor for Multiple-Precision-Arithmetic Computative 25

IP Core of Coprocessor for Multiple-Precision-Arithmetic Com...

引用

25th International conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2018

作者： Rudnicki, Kamil Stefanski, Tomasz P. Department of Reconfigurable Systems Brightelligence Inc. Glasgow United Kingdom Faculty of Electronics Telecommunications and Informatics Gdansk University of Technology Gdansk80-233 Poland

ISBN: (纸本)9788363578138

In this paper, we present an IP core of coprocessor supporting computations requiring integer multiple-precision arithmetic (MPA). Whilst standard 32/64-bit arithmetic is sufficient to solve many computing problems, there are still applications that require higher numerical precision. Hence, the purpose of the developed coprocessor is to support and offload central processing unit (CPU) in such computations. The developed digital circuit of the coprocessor works with integer numbers of precision approaching maximally 32 kbits. Our IP core is developed using the very high speed integrated circuit hardware description language (VHDL) and simulated assuming implementation in field-programmable gate arrays (fpgas). It exchanges data using three 64-bit data buses whereas a code for execution on the coprocessor is fetched from a dedicated 8-bit bus (all buses in AMBA standard - AXI Stream). An instruction set of the coprocessor currently consists of 7 instructions including multiplication, addition and subtraction. The computations can maximally employ 16 registers of the length 32k bits. Simulation results assuming implementation on Zynq system on chip (SoC) show that computations of the factorial (n!) for n=\pmb{1000} take \pmb{326.4}\mu\pmb{\sec}. Such a design currently requires 7982 look-up tables (LUTs), 10400 flip-flops (FFs), 33 block RAMs (BRAMs) and 28 DSP modules. The processor is aimed to provide scalability allowing one to use the developed IP core not only in scientific computing, but also in embedded systems employing encryption based on MPA. © 2018 Department of Microelectronics and Computer Science, Lodz University of technology.

关键词： Table lookup

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Design of a Compact and reconfigurable Onboard Data Handling System

Design of a Compact and Reconfigurable Onboard Data Handling...

引用

IEEE International conference on Big Data and Cloud computing (BdCloud)

作者： Qing Zhou Qingjie Zhao Li Zhou Junshe An Changbin Xue Yuyin Tan Jianing Rao National Space Science Center Chinese Academy of Sciences Beijing China Beijing Institute of Technology Beijing China

ISBN: (纸本)9781728111421;9781728111414

Onboard data handling (OBDH) system is the key to spacecraft avionics. To adapt to the harsh external space environment, traditional onboard data handling system is usually highly expensive, complex and arduous by using high quality components. Design of a compact and reconfigurable onboard data handling system based is proposed in this paper. A NOR Flash with mass storage is designed as the program memory for CPU and SRAM fpgas. The programs of the CPU and SRAM fpgas in this system can still be reconfigurable for the launched satellites. Rad-hard designs from the Software and hardware are adopted in the onboard data handling system to realize the performances of high reliability, anti-SEU(single event upset) effect, software reconfiguration with less mass, volume and cost. Some experimental results are shown at last in the system verification.

关键词： Field programmable gate arrays Random access memory Software Data handling Aerospace electronics Software reliability

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A Dynamically reconfigurable Platform for High-Performance and Low-Power On-Board Processing

A Dynamically Reconfigurable Platform for High-Performance a...

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NASA/ESA conference on Adaptive Hardware and Systems (AHS)

作者： Andrea Guerrieri Sahand Kashani-Akhavan Pasquale Lombardi Bilel Belhadj Paolo Ienne EPFL Processor Architecture Laboratory Lausanne Switzerland Syderal SA Gals Switzerland

fpgas (Field Programmable Gate Array) are an attractive technology for high-speed data processing in space missions due to their unbeatable flexibility and best performance-to-power ratio in comparison to software. However fpgas suffer from 3 major drawbacks: (1) higher programming effort is required with respect to software; (2) hardware resources need to be allocated for each implemented function in contrast to software functions which can be executed on the same processing hardware; and (3) fpgas are required to adopt radiation hardening techniques when deployed in a space environment. This paper presents a reconfigurable platform that demonstrates how modern fpgas can be considered as computing resources like any other, suitable for emerging spatial applications and not subjected to the above-mentioned drawbacks. In particular, we show that large fpgas can be split in different regions containing concurrently-running accelerators which can support the execution of a single or multiple applications. Then, in the same way as software-based multiprogrammed and multithreaded systems can dynamically create, schedule and execute threads, FPGA-based accelerators can be swapped in and out according to scheduling needs by exploiting their dynamic partial reconfiguration capability. A proof of concept cloud detection algorithm for Sentinel-2 multispectral images has been implemented and tested on our platform to validate the system's design principles and performance.

关键词： Field programmable gate arrays Hardware Instruction sets Computer architecture Space missions Runtime

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LinkBlaze: Efficient Global Data Movement for fpgas

LinkBlaze: Efficient Global Data Movement for FPGAs

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Maidee, Pongstorn Kaviani, Alireza Zeng, Kevin Xilinx Res Labs San Jose CA 95124 USA

ISBN: (纸本)9781538637975

FPGA capacity has grown rapidly and emerging applications comprise a large number of compute modules. The communication among these modules and external memory will cause routing congestion in fabric interconnect. This problem is more pronounced with process scaling since the technology is not improving wire resistance. High-speed data compute modules along with faster local storage enable efficient kernels running at 500-800 MHz on the newer devices. FPGA system performance at those high frequencies will require efficient global data movement across the chip from/ to an external memory. We propose a system-level solution for global data movement in fpgas, called LinkBlaze, to address these issues. LinkBlaze leverages both general Network-on-Chip (NoC) techniques and FPGA architecture for reducing resource usage. This work explores different router architectures and provides insights for the user on how to best utilize and share the global links on the FPGA. Our results indicate 640 MHz performance on Ultrascale+ for an optimized 3-port soft NoC. We further extend those results to implement a global data movement overlay operating as high as 1 GHz, by restricting the number of clients and leveraging flexible FPGA placement. Our proposed solution enables 8GB/s system-level throughput in Ultrascale+ for a 64-bit instance, while using underutilized resources in fpgas. Our results indicate how to scale our solution to implement more than 52GB/s access to external memory using 2-3X less fabric resources. We recommend an architecture and a preferred location for our proposed interconnect overlay and intend to make the solution available for the FPGA application community.

关键词： FPGA Interconnect Ultrascale Overlay NoC

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A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays

A reconfigurable memory architecture for system integration ...

引用

2017 International conference on reconfigurable computing and fpgas, ReConFig 2017

作者： Sousa, Éricles Tanase, Alexandru Hannig, Frank Teich, Jürgen Germany

ISBN: (纸本)9781538637975

Coarse-Grained reconfigurable Arrays (CGRAs) have emerged as a powerful solution to speed up computationally intensive applications. Heterogeneous MPSoC architectures containing such reconfigurable accelerators have the advantage of providing greater flexibility, power-efficiency, and high performance. However, CGRAs may suffer from a data access bottleneck. To mitigate this problem, we present a reconfigurable memory architecture for CGRAs. Here, buffers can be configured at runtime to select between different schemes for memory access, i. e., random access memory or pixel buffers. We showcase the benefits to our approach by prototyping a heterogeneous MPSoC architecture containing a RISC processor and a class of CGRAs called tightly coupled processor arrays (TCPAs). The architecture is prototyped in FPGA technology. To communicate with up to 32 processing elements (PEs), the memory architecture utilizes less than 2.5% of slice registers and LUTs available in a Virtex-7 XC7V2000. For digital signal processing applications, we demonstrate that our solution for system integration allows increasing the memory bandwidth utilization in comparison to state-of-the-art solutions for image processing. © 2017 IEEE.

关键词： Memory architecture

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UNIX-Like Operating System Extension for Real-Time FPGA-Based SCCS Support 9

UNIX-Like Operating System Extension for Real-Time FPGA-Base...

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9th IEEE International conference on Intelligent Data Acquisition and Advanced computing Systems - technology and applications (IDAACS)

作者： Melnyk, Anatoliy Melnyk, Viktor Kit, Andriy John Paul II Catholic Univ Lublin Ul Konstantynow 1H P 313 PL-20708 Lublin Poland Lviv Polytech Natl Univ Bandery Str 12 UA-79013 Lvov Ukraine Ostware Serv Ltd Naukova Str 7b-801-802 UA-79060 Lvov Ukraine

ISBN: (纸本)9781538606971

The questions of further implementation of the operating system software means for the real-time FPGA-based self-configurable computer systems support will be discussed in the paper. These computer systems compete with other types of high-performance computer systems due to high speed characteristics of modern field-programmable gate arrays (fpgas) - hardware base of reconfigurable computing environment (RCE), and due to advances in design technology of application-specific processors to be synthesized in RCE. Moreover, in the self-configurable computer systems (SCCS) the labor-intensive and time-consuming works of tasks distribution between the processing units and development of the IP cores required for implementation in the RCE, are fully automated and replaced from the operator to the computer system. Taking into account the necessity of further improvement of computer means performance and expansion of reconfigurable devices application in the Cloud computing and Cyber-Physical Systems (CPS), further development in the field of self-configurable computer systems is a topical challenge of scientific research and engineering.

关键词： self-configurable computer system operating system reconfigurable computing cloud computing cyber-physical system

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BKVex: an Adaptable VLIW Processor and Design Framework for reconfigurable computing Platforms

BKVex: an Adaptable VLIW Processor and Design Framework for ...

引用

International conference on Advanced computing and applications (ACOMP)

作者： Cuong Pham-Quoc Binh Kieu-Do-Nguyen Anh-Vu Dinh-Duc Ho Chi Minh City Univ Technol VNU HCM Ho Chi Minh City Vietnam Vietnam Natl Univ Ho Chi Minh City Vietnam

ISBN: (纸本)9781538606070

reconfigurable computing has been considering as one of the main approaches to utilize billions transistors integrated in a chip in this nanoscale era. In this paper, we introduce our adaptable VLIW processor whose organization is reconfigurable at design time so that the processor is optimized for a particular program or application-domain. Issue-width, the number of registers, instruction and data caches, and functional units availability are reconfigurable parameters. The processor, in all configurations, can function in a 5-stage pipeline model to improve performance. Moreover, we present our design framework that helps users determine an optimized VLIW processor configuration according to requirements of the executed program. The design framework also allows users to implement the VLIW processor on an FPGA-based platform without knowing HDLs. We synthesize the processor in different configurations with four FPGA technologies. The synthesis results show that our processor can work at up to 174.89 MHz with the Xilinx Virtex 7 technology. When compared to NIOS ii RISC-like softcore processor at the same working frequency, our adaptable VLIW processor achieves speed-ups by up to 22.6x.

关键词： FPGA Adaptable VLIW processor Issue-width Processor architecture

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Discrete and Logico-Numerical Control for Dynamic Partial reconfigurable FPGA-Based Embedded Systems: A Case Study

Discrete and Logico-Numerical Control for Dynamic Partial Re...

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Control technology and applications (CCTA),

作者： Soguy Mak-Karé Gueye Gwenaël Delaval Eric Rutten Jean-Philippe Diguet CNRS Univ. Grenoble Alpes Grenoble France CNRS LAB-STICC Lorient France

Embedded systems need to be more and more self-adaptive, in order to better manage their constrained resources, and to better take into account evolutions in their environment and in their computing architecture. They can benefit from Field Programmable Gate Array (FPGA) architectures, which supports Dynamic Partial Reconfiguration (DPR) of the running fonctions, enabling improved performance and power consumption. The reconfigurations need to be decided and controlled in a closed loop. We approach this problem by applying techniques from the area of Supervisory Control for Discrete Event Systems (DES), where the space of configurations at the different levels (application, tasks, hardware platform) are modeled with automata, using the tools Heptagon/BZR and ReaX. This paper contributes with (i) generic modeling of the behaviors and objectives; (ii) applications of Discrete Controller Synthesis (DCS), especially logico-numerical control; (iii) concrete implementation on a FPGA hardware platform for an embedded video processing case study.

关键词： Field programmable gate arrays Task analysis Hardware Computational modeling Contracts Automata Tools

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IP Core of Coprocessor for Multiple-Precision-Arithmetic Computations

IP Core of Coprocessor for Multiple-Precision-Arithmetic Com...

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International conference on Mixed Design of Integrated Circuits and Systems (MIXDES)

作者： Kamil Rudnicki Tomasz P. Stefanski Department of Reconfigurable Systems Brightelligence Inc. Glasgow UK Faculty of Electronics Gdansk University of Technology Gdansk Poland

In this paper, we present an IP core of coprocessor supporting computations requiring integer multiple-precision arithmetic (MPA). Whilst standard 32/64-bit arithmetic is sufficient to solve many computing problems, there are still applications that require higher numerical precision. Hence, the purpose of the developed coprocessor is to support and offload central processing unit (CPU) in such computations. The developed digital circuit of the coprocessor works with integer numbers of precision approaching maximally 32 kbits. Our IP core is developed using the very high speed integrated circuit hardware description language (VHDL) and simulated assuming implementation in field-programmable gate arrays (fpgas). It exchanges data using three 64-bit data buses whereas a code for execution on the coprocessor is fetched from a dedicated 8-bit bus (all buses in AMBA standard - AXI Stream). An instruction set of the coprocessor currently consists of 7 instructions including multiplication, addition and subtraction. The computations can maximally employ 16 registers of the length 32k bits. Simulation results assuming implementation on Zynq system on chip (SoC) show that computations of the factorial (n!) for n=1000 take 326.4 μsec. Such a design currently requires 7982 look-up tables (LUTs), 10400 flip-flops (FFs), 33 block RAMs (BRAMs) and 28 DSP modules. The processor is aimed to provide scalability allowing one to use the developed IP core not only in scientific computing, but also in embedded systems employing encryption based on MPA.

关键词： Coprocessors IP networks Field programmable gate arrays Registers Computational modeling Standards Simulation

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Integrating fpgas: A dynamically reconfigurable FPGA-based grid for high performance computing

Integrating FPGAs: A dynamically reconfigurable FPGA-based g...

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2016 International conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016

作者： Gazzano, Julio Dondo Department of Technology and Information Systems University of Castilla-La Mancha Ciudad Real Spain

ISBN: (纸本)9781509028894

FPGA-based hybrid systems have shown several characteristics that make them very attractive for high performance computing (HPC). The two domains applications deployment capability, the impressive speed-up factors that they are able to achieve, the reduced power consumption, and the easiness and flexibility of the design process with fast iterations between consecutive versions are examples of benefits obtained with their used Along with these features dynamic reconfiguration is an added value that allows swapping in and out a component in run-time without to stop the FPGA. This talk will show an implementation of a complete grid infrastructure for distributed high performance computing based on dynamically reconfigurable fpgas. Besides, a set of services designed to facilitate the application deployment will be described. An example application and a comparison with software implementations will be shown. © 2016 IEEE.

关键词： Field programmable gate arrays (FPGA)

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