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检索条件"任意字段=Conference on Reconfigurable Technology: FPGAs for Computing and Applications II"

共 419 条记录，以下是71-80 订阅

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A multi-functional memory unit with PLA-based reconfigurable decoder

A multi-functional memory unit with PLA-based reconfigurable...

引用

2016 International conference on reconfigurable computing and fpgas, ReConFig 2016

作者： Yahiro, Nobuyuki Liu, Bo Nanri, Atsushi Nakatake, Shigetoshi Takashima, Yasuhiro Chen, Gong University of Kitakyushu Fukuoka808-135 Japan Chengdu University of Information Technology China

ISBN: (纸本)9781509037070

An application-specific usage of memory is an important key in development of embedded systems for IoT devices. A functional memory unit such as content addressable memory (CAM) is a good solution for network-specific applications. This work proposes a novel functional memory unit which can reconfigure a function of the memory decoder. In our reconfigurable mechanism, uni-switch cells are introduced to play an alternative role of a logic or a wire, and are embedded in an SRAM memory array. A set of uni-switches is connected and constitutes a programmable logic array (PLA) unit. The PLA has a suitable advantage for a decoder that the multi-input and multi-output function can be realized with a small area, compared with look-up table (LUT). Hence, an extensional function of the decoder is realized by PLA units inside the memory array, and a combination of PLA units provides potentials to configure various functions for stored data such as sorting, filtering, error correction, and encryption/decryption. In this paper, we present a fundamental architecture of our functional memory unit with PLA units, and demonstrate an implementation of 32-bit full adder and 2-bit counter by using PLA units. © 2016 IEEE.

关键词： Static random access storage

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reconfigurable In-Memory computing with Resistive Memory Crossbar 35

Reconfigurable In-Memory Computing with Resistive Memory Cro...

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35th IEEE/ACM International conference on Computer-Aided Design (ICCAD)

作者： Zha, Yue Li, Jing Univ Wisconsin Elect & Comp Engn 1415 Engn Dr Madison WI 53706 USA

ISBN: (纸本)9781450344661

Driven by recent advances in resistive random-access memory (RRAM), there have been growing interests in exploring alternative computing concept, i.e., in-memory processing, to address the classical von Neumann bottlenecks. Despite of their great promise in improving performance and energy efficiency, most existing works are built on the inherent matrix-vector multiplication capability of RRAM crossbar structure, and thus lack the flexibility to adapt to future market/technology induced changes in data-intensive applications. To address these challenges, we propose an in-memory reconfigurable architecture based on RRAM crossbar structure. For the first time, it achieves a full programmability across computation and storage, and thereby provides more flexibilities of partitioning the hardware resources based on applications' needs. We further develop two complete CAD design flows to facilitate development of applications written in hardware description languages (HDLs) for our architecture, based on: 1) adaption from existing tool set developed for FPGA, 2) a custom tool design optimized towards the new architecture. Our experiments show that, both design flows are effective in exploiting flexible resources offered by our architecture and thus achieves better efficiency than state-of-art fpgas (30% improvement in performance with 66% reduction in area). In addition, compared to adapted design flow, our custom design flow achieves speedup by 3.3x, and further improves mapping quality.

关键词： RRAM reconfigurable In-memory computing

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An FPGA Based reconfigurable IPSec ESP Core suitable for IoT applications 10

An FPGA Based Reconfigurable IPSec ESP Core suitable for IoT...

引用

10th International conference on Sensing technology (ICST)

作者： Rao, Muzaffar Coleman, Joseph Newe, Thomas Univ Limerick Dept Elect & Comp Engn Mobile & Marine Robot Res Ctr Opt Fibre Sensors Res Ctr Limerick Ireland

ISBN: (纸本)9781509007967

This work implements an FPGA (Field Programmable Gate Array) based reconfigurable IPSec ESP core. The IPSec protocol, developed by the IETF (Internet Engineering Task Force) in 1998, is a popular solution to facilitate protection of the data being transferred at the IP layer. IPSec ESP is one of the two main IPSec protocols (AH: Authentication Header and ESP: Encapsulation Security Payload). IPSec ESP is used to provide data confidentiality security services with Authenticity (optional). Implementation of the IPSec is a computing intensive work, that's why hardware implementation of IPSec is a best solution. Here, to design IPSec ESP core an encryption algorithm AES is used. Proposed design also supports ESP-tunnel and ESP-transport mode of operation. This core is tested by applying default length of 576 bytes for an IPv4 datagram and results are reported on Virtex-5 and Virtex-6 fpgas. The proposed IPSec ESP core can be used to provide data confidentiality security to IoT applications.

关键词： FPGA AES IPSec ESP

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Highly Reliable Controller Implementation Using a Network-Based Fully reconfigurable FPGA for Industrial applications

Highly Reliable Controller Implementation Using a Network-Ba...

引用

IEEE International conference on Emerging Technologies and Factory Automation

作者： Gehad I. Alkady Ramez M. Daoud Hassanein H. Amer Ihab Adly Hassan H. Halawa Mohamed B. Abdelhalim Department American University in Cairo (AUC) Electronics and Communications Engineering Cairo Egypt Tegrom Cairo Egypt Electrical and Computer Engineering Department University of British Columbia (UBC) Vancouver Canada College of Computing and Information Technology Arab Academy of Science and Technology and Maritime Transport Cairo Egypt

Fault-Tolerance is currently a very important feature in industrial automation. This paper focuses on Fault-Tolerant FPGA-based controllers for Sensor-to-Actuator Networked Control Systems. A design is proposed that takes advantage of the Dynamic Partial Reconfiguration property inherent in some fpgas. The controller is assumed to consist of a small processor, memory and associated hardware. Several Fault-Tolerance techniques are applied to this generic system and single points of failure are avoided even in the error detection and recovery mechanisms. The fault model considered is single and/or some multiple event upsets. A case study is presented to quantify the increase in reliability of the presented system. Furthermore, the proposed architecture can support FPGA full configuration as well as partial reconfiguration over TCP/IP networks through on-chip configuration network interface with minimal off-chip components.

关键词： Fault-Tolerant Reliability S2A FPGA Dynamic Partial Reconfiguration Networked Control Systems

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Optimal processor interface for CGRA-based accelerators implemented on fpgas

Optimal processor interface for CGRA-based accelerators impl...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Lukas Johannes Jung Christian Hochberger Department for Electrical Engineering and Information Technology Computer Systems Group Darmstadt TU

Coarse Grained reconfigurable Arrays (CGRA) can be used to substantially boost the processing power of embedded applications. They can be included in typical system-on-chip architectures to execute computationally demanding parts of the application. Delegating execution to the CGRA requires the exchange of live in/out variables between the processor core and the CGRA. In this paper we search the optimal interface between the surrounding system and the CGRA with respect to impact on the operating frequency, the used resources and the runtime overhead.

关键词： Registers Context Routing Multiplexing Computer architecture Hardware Clocks

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Energy-aware Service Orchestration based on Temporal reconfigurable Architecture 25

Energy-aware Service Orchestration based on Temporal Reconfi...

引用

25th IEEE International conference on Enabling Technologies - Infrastructure for Collaborative Enterprises (WETICE)

作者： Hosni, Emna Brahmi, Zaki Manouba Univ RIADI GD Lab Manouba Tunisia

ISBN: (纸本)9781509016631

Cloud computing is by far the most cost-effective technology for hosting Internet-scale services and applications. It becomes a valuable contributor and cost-saver for companies with the introduction of orchestration platforms as a Service (OaaS) to perform the services that support a variety of business processes such as BPEL. In this paper we will investigate three issues i) exploiting the minimum of resources to execute a maximum number of processes, ii) preventing possible overload to the server, and iii) minimizing the dynamic energy consumption which becomes one of the main challenges for large-scale computing, such as in cloud data center. As a solution for these challenges we propose a temporal partitioning based on dynamic reconfiguration approach. Our work aims to reduce the dynamic energy consumption. The proposed approach is based on two main steps: 1) Estimate the energy consumption of BPEL processes 2) Temporal and dynamic partitioning of BPEL process based on reconfigurable architecture in order to minimize overall energy consumption on each BPEL process at run time.

关键词： Bpel process Buffer Dynamic energy consumption Temporal partitioning

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Bio-inspired system architecture for energy efficient, BIGDATA computing with application to wide area motion imagery 7

Bio-inspired system architecture for energy efficient, BIGDA...

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7th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2016

作者： Andreou, Andreas G. Figliolia, Tomas Sanni, Kayode Murray, Thomas S. Tognetti, Gaspar Mendat, Daniel R. Molin, Jamal L. Villemur, Martin Pouliquen, Philippe O. Julian, Pedro Etienne-Cummings, Ralph Doxas, Isidoros Department of Electrical and Computer Engineering Johns Hopkins University BaltimoreMD21218 United States BAE Systems ColumbiaMD21046 United States CONICET and Universidad Nacional Del sur Argentina

ISBN: (纸本)9781467378352

In this paper we discuss a brain-inspired system architecture for real-time big velocity BIGDATA processing that originates in large format tiled imaging arrays used in wide area motion imagery ubiquitous surveillance. High performance and high throughput is achieved through approximate computing and fixed point arithmetic in a variable precision (6 bits to 18 bits) architecture. The architecture implements a variety of processing algorithms classes ranging from convolutional networks (Con-vNets) to linear and non-linear morphological processing, probabilistic inference using exact and approximate Bayesian methods and ConvNet based classification. The processing pipeline is implemented entirely using event based neuromorphic and stochastic computational primitives. The system is capable of processing in real-time 160 × 120 raw pixel data running on a reconfigurable computing platform (5 Xilinx Kintex-7 fpgas). The reconfigurable computing implementation was developed to emulate the computational structures for a 3D System on Chip (3D-SOC) that will be fabricated in the 55nm CMOS technology and it has a dual goal: (i) algorithm exploration and (ii) architecture exploration. © 2016 IEEE.

关键词： Fixed point arithmetic

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FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting

FPGA architecture for feed-forward sequential memory network...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Kentaro Orimo Kota Ando Kodai Ueyoshi Masayuki Ikebe Tetsuya Asai Masato Motomura Graduate School of Information Science and Technology Hokkaido University Sapporo Hokkaido Japan

Deep learning is being widely used in various applications, and diverse neural networks have been proposed. A form of neural network, such as the novel feed-forward sequential memory network (FSMN), aims to forecast prospective data by extracting the time-series feature. FSMN is a standard feed-forward neural network equipped with time-domain filters, and it can forecast without recurrent feedback. In this paper, we propose a field-programmable gate-array (FPGA) architecture for this model, and exhibit that the resource does not increase exponentially as the network scale increases.

关键词： Time-domain analysis Neurons Computer architecture Neural networks Temperature measurement Field programmable gate arrays Feature extraction

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The configurable cloud - accelerating hyperscale datacenter services with fpgas

The configurable cloud - accelerating hyperscale datacenter ...

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IEEE International conference on Field-Programmable technology (FPT)

作者： Andrew Putnam Microsoft Research Redmond WA US

ISBN: (纸本)9781509056033

Summary form only given. The Catapult project has brought the power and performance of FPGA-based reconfigurable computing to Microsoft's hyperscale datacenters, accelerating major production cloud applications such as Bing web search and Microsoft Azure, and enabling a new generation of machine learning and artificial intelligence applications. In this talk, I will describe the next generation of the Catapult configurable cloud architecture, show some of the applications have been accelerated by Catapult, and discuss the experiences and lessons learned while bringing up the first applications in the configurable cloud. I will also share stories of the evolution of Catapult - from its origins as a single development kit board through to the hyperscale deployment of hundreds of thousands of fpgas across 15 countries and 5 continents - highlighting insights and experiences that transformed Catapult from a caffeine-fueled PowerPoint presentation into the largest deployment of reconfigurable computing in the world.

关键词： Horn antennas Dipole antennas Lenses Directive antennas Gallium arsenide Silicon

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A multi-functional memory unit with PLA-based reconfigurable decoder

A multi-functional memory unit with PLA-based reconfigurable...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Nobuyuki Yahiro Bo Liu Atsushi Nanri Shigetoshi Nakatake Yasuhiro Takashima Gong Chen The University of Kitakyushu Fukuoka Japan Chengdu University of Information Technology

关键词： Random access memory Micromechanical devices Decoding Switches

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