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A choice of FPGA design for three phase sinusoidal pulse width modulation

A choice of FPGA design for three phase sinusoidal pulse wid...

引用

2016 IEEE International conference on Emerging Technological Trends in computing, Communications and Electrical Engineering, ICETT 2016

作者： Jacob, Teena Krishna, Anjali Padma Suresh, L. Muthukumar, P. Dept. of EEE Noorul Islam University Kanyakumari District Tamil Nadu India Baselios Mathews II College of Engineering Kollam India Dept. of EEE Sree Sastha Institute of Engineering and Technology Chennai India

ISBN: (纸本)9781509037513

A FPGA based three phase sinusoidal pulse width modulator IC is designed. Pulse width modulated dc-ac converters have a broad range of applications in ac motor drives and ac power conditioning systems. The PWM strategy plays important roles in the reduction of harmonics and switching losses in these converters especially in three phase applications. Various modulation strategies, control schemes has been developed in recent years. In this work it is proposed to design FPGA/CPLD based ASIC solution for sinusoidal pulse width modulation generation with reconfigurable technology. It is also proposed to compare different architectures based on number of memories, multipliers and comparators for the generation of SPWM in order to optimize the speed and size of the SPWM generator IC. This SPWM generation is simulated by ModelSim SE 6.3f and synthesis by Xilinx Project Navigator tool. The proposed IC for SPWM generation will facilitate faster but compact solution for three phase voltage source inverter fed drives. © 2016 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Efficient deep neural network acceleration through FPGA-based batch processing

Efficient deep neural network acceleration through FPGA-base...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Thorbjörn Posewsky Daniel Ziener Institute of Embedded Systems Hamburg University of Technology (TUHH) Hamburg Germany

Deep neural networks are an extremely successful and widely used technique for various pattern recognition and machine learning tasks. Due to power and resource constraints, these computationally intensive networks are difficult to implement in embedded systems. Yet, the number of applications that can benefit from the mentioned possibilities is rapidly rising. In this paper, we propose a novel architecture for processing previously learned and arbitrary deep neural networks on FPGA-based SoCs that is able to overcome these limitations. A key contribution of our approach, which we refer to as batch processing, achieves a mitigation of required weight matrix transfers from external memory by reusing weights across multiple input samples. This technique combined with a sophisticated pipelining and the usage of high performance interfaces accelerates the data processing compared to existing approaches on the same FPGA device by one order of magnitude. Furthermore, we achieve a comparable data throughput as a fully featured x86-based system at only a fraction of its energy consumption.

关键词： Neurons Hardware Field programmable gate arrays Biological neural networks Computer architecture Parallel processing Acceleration

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High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform

High-throughput cellular imaging with high-speed asymmetric-...

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International conference on reconfigurable computing and fpgas (ReConFig)

作者： Ho-Cheung Ng Maolin Wang Bob M.F. Chung B. Sharat Chandra Varma Manish Kumar Jaiswal Sam M.H. Ho Kevin K. Tsia Ho Cheung Shum Hayden Kwok-Hay So Department of Computing Imperial College London UK Department of Electrical & Electronic Engineering University of Hong Kong Hong Kong Department of Mechanical Engineering University of Hong Kong Hong Kong Department of Avionics Indian Institute of Space Science and Technology India

Asymmetric-Detection Time-Stretch Optical Microscopy (ATOM) is a recently emerged technology that provides ultra-fast cell imaging with a frame rate up to MHz - orders-of-magnitude higher than any classical imaging systems. However, existing measuring instruments are unable to fully exploit the capability of ATOM. For example, the volume of imaging data-set of ATOM quickly increases beyond the capacity of available onboard buffer of a modern high-speed oscilloscope. This paper presents an open source, FPGA-based solution which serves as a dual role of collecting low-level signals from ATOM frontend as well as processing and transferring data to backing store. Optical signals are sampled by a high-speed analog-to-digital converter and the resulting values are collected by an FPGA. The quantized values received are then further processed and divided into four segments for subsequent data transfer with 10 Gbit Ethernet. Four computing units are attached to these channels with direct connection in order to reliably receive the data for post-processing. Experiments show that, with decent quality images for single-cell analysis, the proposed system can store 10x more dataset than existing high-end oscilloscope. With 8x decrease in equipment cost, the proposed FPGA-based system will definitely be beneficial for many bio imaging applications with ATOM technology such as rare cancer cell imaging and identification.

关键词： Field programmable gate arrays Atom optics Optical imaging Biomedical optical imaging Clocks Optical pulses

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Connect on the fly: Enhancing and prototyping of cycle-reconfigurable modules

Connect on the fly: Enhancing and prototyping of cycle-recon...

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International conference on Field Programmable Logic and applications

作者： Hao Zhou Xinyu Niu Junqi Yuan Lingli Wang Wayne Luk School of Microelectronics Fudan University China Dept. of Computing Imperial College London UK

This paper introduces cycle-reconfigurable modules that enhance FPGA architectures with efficient support for dynamic data accesses: data accesses with accessed data size and location known only at runtime. The proposed module adopts new reconfiguration strategies based on dynamic FIFOs, dynamic caches, and dynamic shared memories to significantly reduce configuration generation and routing complexity. We develop a prototype FPGA chip with the proposed cycle-reconfigurable module in the SMIC 130-nm technology. The integrated module takes less than the chip area of 39 CLBs, and reconfigures thousands of runtime connections in 1.2 ns. applications for large-scale sorting, sparse matrix-vector multiplication, and Memcached are developed. The proposed modules enable 1.4 and 11 times reduction in area-delay product compared with those applications mapped to previous architectures and conventional fpgas.

关键词： Runtime Clocks Field programmable gate arrays Customer relationship management Routing Hardware System-on-chip

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An FPGA based reconfigurable IPSec ESP core suitable for IoT applications

An FPGA based reconfigurable IPSec ESP core suitable for IoT...

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International conference on Sensing technology, ICST

作者： Muzaffar Rao Joseph Coleman Thomas Newe Department of Electronic and Computer Engineering University of Limerick Limerick Ireland

ISBN: (纸本)9781509007974

This work implements an FPGA (Field Programmable Gate Array) based reconfigurable IPSec ESP core. The IPSec protocol, developed by the IETF (Internet Engineering Task Force) in 1998, is a popular solution to facilitate protection of the data being transferred at the IP layer. IPSec ESP is one of the two main IPSec protocols (AH: Authentication Header and ESP: Encapsulation Security Payload). IPSec ESP is used to provide data confidentiality security services with Authenticity (optional). Implementation of the IPSec is a computing intensive work, that's why hardware implementation of IPSec is a best solution. Here, to design IPSec ESP core an encryption algorithm AES is used. Proposed design also supports ESP-tunnel and ESP-transport mode of operation. This core is tested by applying default length of 576 bytes for an IPv4 datagram and results are reported on Virtex-5 and Virtex-6 fpgas. The proposed IPSec ESP core can be used to provide data confidentiality security to IoT applications.

关键词： Protocols IP networks Encryption Field programmable gate arrays Authentication Payloads

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reconfigurable in-memory computing with resistive memory crossbar

Reconfigurable in-memory computing with resistive memory cro...

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IEEE International conference on Computer-Aided Design

作者： Yue Zha Jing Li Electrical and Computer Engineering University of Wisconsin Madison WI

ISBN: (纸本)9781509034215

Driven by recent advances in resistive random-access memory (RRAM), there have been growing interests in exploring alternative computing concept, i.e., in-memory processing, to address the classical von Neumann bottlenecks. Despite of their great promise in improving performance and energy efficiency, most existing works are built on the inherent matrix-vector multiplication capability of RRAM crossbar structure, and thus lack the flexibility to adapt to future market/technology induced changes in data-intensive applications. To address these challenges, we propose an in-memory reconfigurable architecture based on RRAM crossbar structure. For the first time, it achieves a full programmability across computation and storage, and thereby provides more flexibilities of partitioning the hardware resources based on applications' needs. We further develop two complete CAD design flows to facilitate development of applications written in hardware description languages (HDLs) for our architecture, based on: 1) adaption from existing tool set developed for FPGA, 2) a custom tool design optimized towards the new architecture. Our experiments show that, both design flows are effective in exploiting flexible resources offered by our architecture and thus achieves better efficiency than state-of-art fpgas (30% improvement in performance with 66% reduction in area). In addition, compared to adapted design flow, our custom design flow achieves speedup by 3.3×, and further improves mapping quality.

关键词： Field programmable gate arrays Random access memory Routing Hardware Arrays Bars

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Energy-Aware Service Orchestration Based on Temporal reconfigurable Architecture

Energy-Aware Service Orchestration Based on Temporal Reconfi...

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IEEE International Workshop on Enabling Technologies: Infrastructure for Collaborative Enterprises (WET ICE)

作者： Emna Hosni Zaki Brahmi RIADI-GD Laboratory Manouba University Tunisia

Cloud computing is by far the most cost-effective technology for hosting Internet-scale services and applications. It becomes a valuable contributor and cost-saver for companies with the introduction of orchestration platforms as a Service (OaaS) to perform the services that support a variety of business processes such as BPEL. In this paper we will investigate three issues i) exploiting the minimum of resources to execute a maximum number of processes, ii) preventing possible overload to the server, and iii) minimizing the dynamic energy consumption which becomes one of the main challenges for large-scale computing, such as in cloud data center. As a solution for these challenges we propose a temporal partitioning based on dynamic reconfiguration approach. Our work aims to reduce the dynamic energy consumption. The proposed approach is based on two main steps: 1) Estimate the energy consumption of BPEL processes 2) Temporal and dynamic partitioning of BPEL process based on reconfigurable architecture in order to minimize overall energy consumption on each BPEL process at run time.

关键词： Energy consumption Partitioning algorithms Cloud computing Engines Servers Computer architecture Buffer storage

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Efficient and flexible NoC-based group communication for secure MPSoCs

Efficient and flexible NoC-based group communication for sec...

引用

International conference on reconfigurable computing and fpgas, ReConFig 2015

作者： Sepúlveda, Johanna Flórez, Daniel Gogniat, Guy Institute for Security in Information Technology Technical University of Munich Germany Lab-STICC South Brittany University France

ISBN: (纸本)9781467394062

In order to improve the performance, embedded applications are distributed on several IP cores of Multiprocessors Systems-on-Chip (MPSoCs). Such a strategy forces the peer interaction among the different computation components, which have to exchange data through the Networkson- Chip (NoC). For applications for which security is an important concern, data exchanged among the IPs must remain confidential. Security zones are built to wrap the sensitive IPs and guarantee their protection from malicious applications. Several approaches have been proposed to create the security zones. However, due the ever-changing nature of these zones, the impact of creating and destroying the zones on the system performance is not negligible. In this work, for the first time we propose the implementation of smart security zones that efficiently create security zones by combining robust contributory group key agreement protocols and the NoC routing. Our approach can efficiently create, modify or remove continuous and disrupted security zones. We evaluate our approach under synthetic traffic patterns and the execution of SPLASH2 benchmarks. We show that our architecture is able to manage dynamic security zones while presenting low impact on the performance and cost of MPSoCs. © 2015 IEEE.

关键词： Network-on-chip

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Designing customized ISA processors using high level synthesis

Designing customized ISA processors using high level synthes...

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International conference on reconfigurable computing and fpgas, ReConFig 2015

作者： Skalicky, Sam Ananthanarayana, Tejaswini Lopez, Sonia Lukowiak, Marcin Xilinx Inc. San JoseCA United States Rochester Institute of Technology RochesterNYUSA United States

ISBN: (纸本)9781467394062

In this paper we propose a new degree of flexibility for soft processor design in which only the instructions relevant to the task at hand are implemented as a subset of the Instruction Set Architecture (ISA). These customized processors execute software kernels in the usual way, yet can be implemented with a fraction of the hardware resources used by other full- ISA soft processor cores. We present a design methodology for such customized ISA processors where the functional description of the processor is written in a high level language and the hardware implementation is obtained using high level synthesis (HLS) tools. We investigate the potential and limitations of the HLS tools to take processor simulator-like implementations in C/C++ and produce functional hardware processor architectures. We apply this methodology to two relevant applications -a basic linear algebra application and a cryptographic application- due to their distinct features. Our results demonstrate that these customized processors utilize significantly less hardware resources than those required by Xilinx MicroBlaze with reasonable performance degradation using HLS generated hardware exclusively. © 2015 IEEE.

关键词： C++ (programming language)

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Customizable Heterogeneous Acceleration for Tomorrow's High-Performance computing 17

Customizable Heterogeneous Acceleration for Tomorrow's High-...

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2015 IEEE 17th International conference on High Performance computing and Communications (HPCC)

作者： Cilardo, Alessandro Flich, Jose Gagliardi, Mirko Gavila, Rafael T. Univ Naples Federico II DIETI Naples Italy Univ Politecn Valencia GAP Valencia Spain

ISBN: (纸本)9781479989379

High-performance computing as we know it today is experiencing unprecedented changes, encompassing all levels from technology to use cases. This paper explores the adoption of customizable, deeply heterogeneous manycore systems for future QoS-sensitive and power-efficient high-performance computing. At the heart of the proposed architecture is a NoC-based manycore system embracing medium-end CPUs, GPU-like processors, and reconfigurable hardware regions. The paper discusses the high-level design principles inspiring this innovative architecture as well as the key role that heterogeneous acceleration, ranging from multicore processors and GPUs down to fpgas, might play for tomorrow's high-performance computing.

关键词： field programmable gate arrays graphics processing units multiprocessing systems network-on-chip parallel processing power aware computing quality of service FPGA GPU-like processors NoC-based many-core system QoS-sensitive computing customizable heterogeneous acceleration heterogeneous acceleration heterogeneous manycore systems high-level design principles high-performance computing innovative architecture medium-end CPU multicore processors power-efficient high-performance computing reconfigurable hardware regions Acceleration Computer architecture Field programmable gate arrays Hardware Program processors Quality of service Registers Field programmable gate arrays High Performance computing Quality of service power aware computing Program processors Multiprocessing systems network-on-chip Computer Architecture Registers acceleration PARALLEL PROCESSING (COMPUTERS) Multi-core processors Computer hardware Graphics Processing Unit

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