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BiDSRS plus : Resource Efficient reconfigurable Real Time Bidirectional Super Resolution System for fpgas

IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS 2025年第1期15卷 120-132页

作者： Al Amin, Rashed Obermaisser, Roman Univ Siegen Inst Embedded Syst D-57076 Siegen Germany

Super-resolution (SR) systems represent a rapidly advancing area within Information and Communication technology (ICT) due to their significant applications in computer vision and visual communication. Integrating SR systems with Deep Neural Networks (DNNs) is a widely adopted method for leveraging faster and improved image reconstruction. However, the real-time computational demands, extensive energy overhead and the huge memory footprints associated with DNN-based SR systems limit their throughput and scalability. Field-programmable gate arrays (fpgas) present a viable and promising solution for exploring the structure and architecture of SR systems due to their reconfigurable nature and parallel computing capabilities. The existing FPGA-based solutions can effectively reduce the computational latency in SR systems, they often result in higher resource and energy consumption. Besides, the traditional SR techniques generally focus on either upscaling or downscaling images or videos without offering any scaling reconfigurability. To address these limitations, this paper introduces BiDSRS+, a novel FPGA based resource-efficient and reconfigurable real-time SR system using modified bicubic interpolation method. In addition, BiDSRS+ supports both upscaling and downscaling of images and videos, enhancing its versatility. Evaluations conducted on the Xilinx ZCU 102 FPGA board reveal substantial resource savings, with reductions of 44x LUT, 31x BRAM, and 35x DSP utilization compared to state-of-the-art DNN-based SR systems, albeit with a trade-off in throughput of 0.5x. Furthermore, when compared to leading algorithm-based SR systems, BiDSRS+ achieves reductions of 5.8x LUT, 1.75x BRAM, and 2.3x Power consumption, without compromising the throughput. Due to its high resource efficiency and reconfigurability with a throughput of 4K@60 FPS, BiDSRS+ offers significant advantages in promoting sustainable and energy-efficient green video communication.

关键词： Bicubic interpolation fpgas reconfigurable reconfigurable super-resolution super-resolution super-resolution

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A Survey on Architectures, Hardware Acceleration and Challenges for In-Network computing

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ACM TRANSACTIONS ON reconfigurable technology AND SYSTEMS 2025年第1期18卷 1-34页

作者： Nickel, Matthias Goehringer, Diana Tech Univ Dresden Dresden Germany Tech Univ Dresden Ctr Tactile Internet Human Loop CeTI Dresden Germany

By moving data and computation away from the end user to more powerful servers in the cloud or to cloudlets at the edge, end user devices only need to compute locally for small amounts of data and when low latency is required. However, with the advent of 6G and Internet-of-Everything, the demand for more powerful networks continues to grow. The introduction of Software-Defined Networking and Network Function Virtualization has allowed us to rethink networks and use them for more than just routing data to servers. In addition, the use of more powerful network devices is bringing new life to the concept of active networks in the form of in-network computing. In-Network computing provides the ability to move applications into the network and process data on programmable network devices as they are transmitted. In this work, we provide an overview of in-network computing and its enabling technologies. We take a look at the programmability and different hardware architectures for SmartNICs and switches, focusing primarily on accelerators such as fpgas. We discuss the state of the art and challenges in this area, and look at CGRAs, a class of hardware accelerators that have not been widely discussed in this context.

关键词： In-Network computing Software-Defined Networking FPGA CGRA SoC

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Self-aware Reliable and reconfigurable computing Systems - An Overview

Self-aware Reliable and Reconfigurable Computing Systems - A...

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1st International conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Goehringer, Diana Podlubne, Ariel Vargas, Fabian Krstic, Milos Tech Univ Dresden Chair Adapt Dynam Syst Dresden Germany IHP Leibniz Inst Innovat Mikroelekt Frankfurt Oder Germany Univ Potsdam Potsdam Germany

ISBN: (纸本)9798350364613;9798350364606

In demanding environments like space, avionics or robotics, computing systems face challenges affecting their lifetime and reliability. Traditional approaches like static hardware redundancy prove ineffective for modern, complex systems. This work presents an overview of self-aware, reliable, and reconfigurable computing systems leveraging Field Programmable Gate Arrays (fpgas). Despite increasing application demands, FPGA resources remain limited, posing challenges in implementing static redundancy alongside high performance and energy efficiency. Addressing these challenges requires innovative resilience concepts, emphasizing adaptability, reliability, and energy optimization. This paper surveys existing literature and identifies open challenges in achieving resilient computing systems for demanding applications.

关键词： reconfigurable computing reliability

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Performance Modeling and Scalability Analysis of Stream computing in ESSPER FPGA Clusters 22

Performance Modeling and Scalability Analysis of Stream Comp...

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22nd International conference on Field Programmable technology (ICFPT)

作者： Miyagi, Ryota Yasudo, Ryota Sano, Kentaro Takase, Hideki Univ Tokyo Tokyo Japan Kyoto Univ Kyoto Japan RIKEN Kobe Hyogo Japan

ISBN: (纸本)9798350359114

ESSPER is a flexible and scalable FPGA cluster system designed for reconfigurable HPC, with customizability, scalability, and interoperability with existing HPC systems. The inherent characteristics of ESSPER make it a superior alternative for achieving highly scalable computing solutions, particularly for compute-intensive applications such as numerical simulations and machine learning. However, constraints in communication bandwidth or latency can impact performance and scalability. This paper builds upon a previous performance model study to analyze performance modeling and scalability of streaming computation using a 1D ring of cascaded fpgas with high-speed, low-latency communication links in ESSPER. For evaluation and verification, we implemented a simple vector addition on ESSPER. The Result indicates that measured performance metrics closely align with predictions from the performance model. This model can also be used to estimate performance for other ESSPER applications.

关键词： streaming computing scalability multiple fpgas high-performance computing.

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Meta-Heuristic Optimization of Custom Heterogeneous Blocks defined eFPGA Design 38

Meta-Heuristic Optimization of Custom Heterogeneous Blocks d...

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38th International conference on VLSI Design and International conference on Embedded Systems

作者： Bhargav, D., V Pradyumna, G. Rao, Madhav IIIT Bangalore Bangalore Karnataka India

ISBN: (纸本)9798331522452;9798331522445

Modern Field-Programmable Gate Arrays (fpgas) are highly versatile, with reconfigurable logic functionality that allows designers to create custom designs. Unlike traditional fixed-function integrated circuits, fpgas are reconfigured multiple times to perform different tasks, making them ideal for various applications. An Embedded FPGA (eFPGA) takes the concept of an FPGA and integrates it as an IP core within a larger System-on-Chip (SoC) or Application-Specific Integrated Circuit (ASIC). The proposed work employs Non-dominated Sorting Genetic Algorithm-II (NSGA-II) to evolve efficient and high-performing eFPGA architectures with reduced critical path delay and power defined by a sufficient number of Configurable Logic Blocks (CLBs), custom Digital Signal Processors (DSPs) and Block RAM (BRAMs) for targetting workload under consideration. As a result, this work presents a well-balanced eFPGA architecture layout obtained for four workloads equipped with different numbers of heterogeneous and configurable logic blocks. The results showed a significant improvement of 44.62% in hardware parameters.

关键词： eFPGA VTR OpenFPGA NSGA-II Secure Silicon FPGA Layout reconfigurable computing

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Near-memory computing on fpgas with 3D-stacked Memories: applications, Architectures, and Optimizations

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ACM TRANSACTIONS ON reconfigurable technology AND SYSTEMS 2023年第1期16卷 1-32页

作者： Iskandar, Veronia Abd El Ghany, Mohamed A. Goehringer, Diana Adapt Dynam Syst Nothnitzer Str 46 D-01062 Dresden Germany German Univ Cairo Elect Dept Cairo 11835 Egypt Tech Univ Darmstadt Merckstr 25 D-64283 Darmstadt Germany

The near-memory computing (NMC) paradigm has transpired as a promising method for overcoming the memory wall challenges of future computing architectures. Modern systems integrating 3D-stacked DRAM memory can be leveraged to prevent unnecessary data movement between the main memory and the CPU. FPGA vendors have started introducing 3D memories to their products in an effort to remain competitive on bandwidth requirements of modern memory-intensive applications. Recent NMC proposals target various types of data processing workloads such as graph processing, MapReduce, sorting, machine learning, and database analytics. In this article, we conduct a literature survey on previous proposals of NMC systems on fpgas integrated with 3D memories. By leveraging the high bandwidth offered from such memories together with specifically designed hardware, FPGA architectures have become a competitor to GPU solutions in terms of speed and energy efficiency. Various FPGA-based NMC designs have been proposed with software and hardware optimization methods to achieve high performance and energy efficiency. Our review investigates various aspects of NMC designs such as platforms, architectures, workloads, and tools. We identify the key challenges and open issues with future research directions.

关键词： Near-memory computing 3D stacking FPGA architectures high-bandwidth memory

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ELEVATE: Optimal scheduling of time-sensitive tasks on the heterogeneous reconfigurable Edge 32

ELEVATE: Optimal scheduling of time-sensitive tasks on the h...

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32nd International conference on Network Protocols

作者： Hoyer, Ingo Zaarour, Tarek Khalid, Ahmed Utz, Alexander Seidl, Karsten Brown, Ken Zahran, Ahmed H. Fraunhofer IMS Duisburg Germany Dell Technol Dell Res Dublin Ireland Univ Duisburg Essen Dept Elect Components & Circuits Duisburg Germany Univ Coll Cork UCC Sch Comp Sci & Informat Technol Cork Ireland

ISBN: (纸本)9798350351712;9798350351729

Edge computing is evolving to include heterogeneous compute nodes with distinct characteristics. Graphic processing units (GPU) and field-programmable gate arrays (FPGA) can execute demanding deep learning (DL) tasks while meeting the deadlines of time-sensitive applications. However, fpgas require reconfiguration to execute different tasks. In this paper, we first demonstrate that fpgas can be reconfigured in real-time. Additionally, we propose ELEVATE as a novel scheduling algorithm for reconfigurable heterogeneous edge computing platforms targeting Industry 4.0 post-production quality control. ELEVATE design focusses on optimising the reconfiguration of the FPGA unit for heterogeneous quality inspection tasks. Our simulations indicate that ELEVATE reduces task waiting time by up to two orders of magnitude and achieves energy savings of up to 25% compared to a statically configured FPGA unit.

关键词： Scheuduling FPGA HLS RISC-V offloading

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Event-based vision on fpgas - a survey 27

Event-based vision on FPGAs - a survey

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27th Euromicro conference on Digital System Design

作者： Kryjak, Tomasz AGH Univ Krakow Embedded Vis Syst Grp Krakow Poland

ISBN: (纸本)9798350380392;9798350380385

In recent years there has been a growing interest in event cameras, i.e. vision sensors that record changes in illumination independently for each pixel. This type of operation ensures that acquisition is possible in very adverse lighting conditions, both in low light and high dynamic range, and reduces average power consumption. In addition, the independent operation of each pixel results in low latency, which is desirable for robotic solutions. Nowadays, Field Programmable Gate Arrays (fpgas), along with general-purpose processors (GPPs/CPUs) and programmable graphics processing units (GPUs), are popular architectures for implementing and accelerating computing tasks. In particular, their usefulness in the embedded vision domain has been repeatedly demonstrated over the past 30 years, where they have enabled fast data processing (even in real-time) and energy efficiency. Hence, the combination of event cameras and reconfigurable devices seems to be a good solution, especially in the context of energy-efficient real-time embedded systems. This paper gives an overview of the most important works, where fpgas have been used in different contexts to process event data. It covers applications in the following areas: filtering, stereovision, optical flow, acceleration of AI-based algorithms (including spiking neural networks) for object classification, detection and tracking, and applications in robotics and inspection systems. Current trends and challenges for such systems are also discussed.

关键词： event cameras dynamic vision sensors DVS reconfigurable devices FPGA embedded vision survey

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Efficient Hardware Acceleration of Spiking Neural Networks using FPGA: Towards Real-Time Edge Neuromorphic computing 99

Efficient Hardware Acceleration of Spiking Neural Networks u...

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IEEE 99th Vehicular technology conference (VTC-Spring)

作者： El Maachi, Soukaina Chehri, Abdellah Saadane, Rachid Hassania Sch Publ Works EHTP Intelligent Syst & Sensor Networks SIRC Casablanca Morocco Royal Mil Coll Canada Dept Math & Comp Sci Kingston ON Canada

ISBN: (纸本)9798350387414

This paper examines the critical function of Field-Programmable Gate Arrays (fpgas) in speeding Spiking Neural Networks (SNNs) for real-time edge neuromorphic computing. Our work systematically evaluates the integration of FPGA technology for the optimization and speeding of SNN models. The analysis covers the power efficiency, low latency processing, and parallelism that are intrinsic benefits of fpgas, emphasizing their relevance for edge computing applications. We discuss the smooth transfer of trained SNN models to FPGA platforms. Using an extensive analysis of state-of-the-art architectures, we demonstrate the efficiency benefits of using FPGA to accelerate SNNs. We derive more insights into the real-world applications of this FPGA-SNN integration in various fields. The analysis supports advances in edge computing and neuromorphic processing paradigms by adding to the collective knowledge of how FPGA enhances the real-time processing capabilities of Spiking Neural Networks.

关键词： Spiking Neural Networks Edge computing FPGA Artificial Intelligence Memory Optimization

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Partitioning Large-Scale, Multi-FPGA applications for the Data Center 33

Partitioning Large-Scale, Multi-FPGA Applications for the Da...

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33rd International conference on Field-Programmable Logic and applications (FPL)

作者： Mazraeli, Mohammadmahdi Gao, Yu Chow, Paul Univ Toronto Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9798350341515

With the deployment of fpgas in a data center, there is the opportunity to build large multi-FPGA applications. In this paper, we design a partitioner to address the problem of efficiently assigning the various tasks of a large multi-FPGA application to individual network-connected fpgas according to constraints that consider resource usage, communication bandwidth and communication latency. By using simulated annealing, we can modify the cost function as new objectives and constraints are determined. We build on the Galapagos multi-FPGA platform by introducing a multi-die shell to extend Galapagos to more recent FPGA boards and design the partitioner to work on any collection of single- and multi-die fpgas. Finally, We evaluate the new shell and partitioner using micro-benchmarks and analyze the partitioning of a real-world multi-FPGA application, a Transformer model.

关键词： FPGA reconfigurable computing Partitioning

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