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检索条件"任意字段=Conference on Reconfigurable Technology - FPGAs for Computing and Applications"

共 2962 条记录，以下是101-110 订阅

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Single Transistor Analog Building Blocks: Exploiting Back-Bias reconfigurable Devices 21

Single Transistor Analog Building Blocks: Exploiting Back-Bi...

引用

21st IEEE Interregional NEWCAS conference (NEWCAS)

作者： Bhattacharjee, Niladri Reuter, Maximilian Hofmann, Klaus Mikolajick, Thomas Trommer, Jens NaMLab GGmbH Nothnitzer Str 64a D-01187 Dresden Germany Tech Univ Darmstadt Integrated Elect Syst Lab Merckstr 25 D-64283 Darmstadt Germany Tech Univ Dresden Nanoelect Nothnitzer Str 64 D-01187 Dresden Germany

ISBN: (纸本)9798350300246

reconfigurable Field Effect Transistors (RFETs) combine P-FET and N-FET properties on a single device, enabling the development of new circuit applications. In this paper, we present SPICE simulations of analog building blocks using a Verilog-A Table Model of a new RFET variant, called Back-Bias RFETs (BB-RFETs). The Verilog-A look-up model is extracted from TCAD simulations based on a previously fabricated and measured BB-RFET device on a 22 nm FDSOI platform. The model is verified to mimic the experimentally observed analog circuit behaviours such as frequency doubling and phase shifting from a single transistor setup. In addition, utilizing the reconfiguration between three operational modes, a newly conceived reconfigurable-rectifier is proposed which can be dynamically switched between half-wave rectifier and full-wave rectifier. Both the model and the newly designed circuit building blocks, therefore, aim to inspire circuit designers to utilize this emerging technology for future computing.

关键词： reconfigurable Field Effect Transistors Back-Bias TCAD Cadence Virtuoso Analog Circuits 22 nm FDSOI

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RIS-assisted MEC Computation Offloading for IoVT Networks 14

RIS-assisted MEC Computation Offloading for IoVT Networks

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14th International conference on Information and Communication technology Convergence, ICTC 2023

作者： Widiyanti, Daniar Estu Shin, Soo Young Kumoh National Institute of Technology Dept. of It Convergence Engineering Gumi Korea Republic of

ISBN: (纸本)9798350313277

The Internet of Things (IoT) encompasses a wide range of applications;despite that, some challenges persist and require further research and development. One such challenge is encountered in sensing devices, particularly in Internet of Video Things (IoVT) applications that demand high-capacity wireless transmission. These applications face limitations in computational capability and energy consumption of users, posing significant obstacles to overcome. Mobile edge computing (MEC) has gained attention as it offers potential solutions by offloading complex tasks to assist users. However, the line-of-sight (LoS) issue between users and base stations (BS) caused by blocking objects remains a challenge in MEC. To address latency challenges in IoVT communication affected by obstacles, a collaborative framework between reconfigurable intelligence surfaces (RIS) and task offloading techniques in MEC, specifically in IoVT networks, is proposed. This collaboration aims to optimize the performance and efficiency of IoVT systems by harnessing the combined advantages of RIS and task offloading strategies. © 2023 IEEE.

关键词： internet of video things (IoVT) mobile edge computing (MEC) reconfigurable intelligence surfaces (RIS) task offloading

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Design and Implementation of SSSP Accelerator based-on reconfigurable and Programmable computing Array 6

Design and Implementation of SSSP Accelerator based-on Recon...

引用

6th International conference on Artificial Intelligence and Pattern Recognition, AIPR 2023

作者： Deng, Junyong Deng, Jingwen Xie, Xiaoyan Zhang, Pan Wang, Junjie Zhou, Kai Xi'an University of Posts and Telecommunications China Xi'an University of Science and Technology China

ISBN: (纸本)9798400707674

Most of the existing researches only implement one SSSP algorithm, which cannot fit the diversity of applications, since different applications demand implementations with different efficiency and flexibility. The conflict between the requirements of applications and fixed design of accelerators are still one of the main problems currently faced. The reconfigurable array processor can well ease the above problem due to its property of accommodating both flexibility and efficiency. In this paper, we propose an accelerator based on APR-16, a reconfigurable and programmable computing array to realize the Dijkstra algorithm and the Bellman-Ford algorithm for SSSP, which can switch between the two algorithms when facing different graph data. To deal with the problem of graph data's poor locality, preserving node attributes in the frame buffer is proposed to reduce redundant operations in the computing process. To deal with the problem of an unbalanced load, a parallel mapping scheme for the Dijkstra algorithm and Bellman-Ford algorithm is proposed to reduce the impact of an unbalanced load. According to experimental results, we can improve Bellman- Ford's energy efficiency in comparison to the GPU platform by 22 times and the Dijkstra algorithm's energy efficiency by 15 times. © 2023 ACM.

关键词： Energy efficiency

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Comparative Analysis of Parallel and Cascaded Architectures for the Realization of High-Speed FIR Filters with FPGA 5

Comparative Analysis of Parallel and Cascaded Architectures ...

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5th International conference on Inventive Research in computing applications, ICIRCA 2023

作者： Kumari, Apurva Mahidhar, Lolla Manideep, Kotha Mounika, Kodali B v Raju Institute of Technology Dept. of Ece Narsapur India

ISBN: (纸本)9798350321425

This research work presents a detailed analysis on the design and implementation of parallel and cascade topologies in addition to the realization of high-speed FIR filters using fpgas. An FPGA-based FIR filter's design, implementation, and verification using Verilog HDL are thoroughly analyzed. It is demonstrated that the filter's hardware implementation is effective in terms of clock frequency, utilization of resources, and latency. The architectures are also contrasted, and their benefits and shortcomings are discussed. The parallel architecture is better suitable for high-speed FIR filters than the cascade architecture, according to implementation findings on a Xilinx Spartan-3E FPGA and a VIRTEX FPGA. © 2023 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Energy Efficient Design of Coarse-Grained reconfigurable Architectures: Insights, Trends and Challenges 21

Energy Efficient Design of Coarse-Grained Reconfigurable Arc...

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21st International conference on Field-Programmable technology (ICFPT)

作者： Aliagha, Ensieh Goehringer, Diana Tech Univ Dresden Chair Adapt Dynam Syst Dresden Germany

ISBN: (数字)9781665453363

ISBN: (纸本)9781665453363

Coarse-Grained reconfigurable Architectures (CGRAs) are promising solutions to achieve more performance with the end of Moore's law. Thanks to word-level programmability, they are more energy-efficient compared to fpgas. Although ASICs can minimize energy, they suffer from high Non-Recurring Engineering (NRE) costs and inflexibility. CGRAs provide near ASIC energy efficiency and are deployed in the literature to accelerate low-power and high-performance applications. However, focusing on low-power CGRAs is crucial as a high volume of data should be processed on a resource-constrained device by the development of IoT and Machine Learning applications. This survey has reviewed and categorized CGRA architectures from processing elements, interconnect networks, and memory points of view and derived guidelines for energy-efficient CGRA design.

关键词： Coarse-Grained reconfigurable Architectures (CGRAs) Energy Efficiency Signal Processing Machine Learning

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SpecHD: Hyperdimensional computing Framework for FPGA-based Mass Spectrometry Clustering

SpecHD: Hyperdimensional Computing Framework for FPGA-based ...

引用

27th Design, Automation and Test in Europe conference and Exhibition (DATE)

作者： Pinge, Sumukh Xu, Weihong Kang, Jaeyoung Zhang, Tianqi Moshiri, Niema Bittremieux, Wout Rosing, Tajana Univ Calif San Diego La Jolla CA 92093 USA Univ Antwerp B-2000 Antwerp Belgium

ISBN: (纸本)9798350348606;9783981926385

Mass spectrometry-based proteomics is a key enabler for personalized healthcare, providing a deep dive into the complex protein compositions of biological systems. This technology has vast applications in biotechnology and biomedicine but faces significant computational bottlenecks. Current methodologies often require multiple hours or even days to process extensive datasets, particularly in the domain of spectral clustering. To tackle these inefficiencies, we introduce SpecHD, a hyperdimensional computing (HDC) framework supplemented by an FPGA-accelerated architecture with integrated near-storage preprocessing. Utilizing streamlined binary operations in an HDC environment, SpecHD capitalizes on the low-latency and parallel capabilities of fpgas. This approach markedly improves clustering speed and efficiency, serving as a catalyst for real-time, high-throughput data analysis in future healthcare applications. Our evaluations demonstrate that SpecHD not only maintains but often surpasses existing clustering quality metrics while drastically cutting computational time. Specifically, it can cluster a large-scale human proteome dataset-comprising 25 million MS/MS spectra and 131 GB of MS data-in just 5 minutes. With energy efficiency exceeding 31x and a speedup factor that spans a range of 6x to 54x over existing state-of-the-art solutions, SpecHD emerges as a promising solution for the rapid analysis of mass spectrometry data with great implications for personalized healthcare.

关键词： Mass spectrometry Proteomics Spectral Clustering HD computing FPGA Personalized Healthcare

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ELEVATE: Optimal Scheduling of Time-Sensitive Tasks on the Heterogeneous reconfigurable Edge

ELEVATE: Optimal Scheduling of Time-Sensitive Tasks on the H...

引用

International conference on Network Protocols

作者： Ingo Hoyer Tarek Zaarour Ahmed Khalid Alexander Utz Karsten Seidl Ken Brown Ahmed H. Zahran Fraunhofer IMS Duisburg Germany Dell Research Dell Technologies Ireland Department of Electronic Components and Circuits University of Duisburg-Essen Duisburg Germany School of Computer Science & Information Technology University College Cork (UCC) Ireland

ISBN: (数字)9798350351712

ISBN: (纸本)9798350351729

Edge computing is evolving to include heterogeneous compute nodes with distinct characteristics. Graphic processing units (GPU) and field-programmable gate arrays (FPGA) can execute demanding deep learning (DL) tasks while meeting the deadlines of time-sensitive applications. However, fpgas require reconfiguration to execute different tasks. In this paper, we first demonstrate that fpgas can be reconfigured in real-time. Additionally, we propose ELEVATE as a novel scheduling algorithm for reconfigurable heterogeneous edge computing platforms targeting Industry 4.0 post-production quality control. ELEVATE design focusses on optimising the reconfiguration of the FPGA unit for heterogeneous quality inspection tasks. Our simulations indicate that ELEVATE reduces task waiting time by up to two orders of magnitude and achieves energy savings of up to 25 % compared to a statically configured FPGA unit.

关键词： Protocols Scheduling algorithms Graphics processing units Quality control Optimal scheduling Inspection Real-time systems Fourth Industrial Revolution Field programmable gate arrays Edge computing

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Q2Logic: A Coarse-Grained FPGA Overlay targeting Schrödinger Quantum Circuit Simulations

Q2Logic: A Coarse-Grained FPGA Overlay targeting Schrödinge...

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2023 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2023

作者： Podobas, Artur KTH Royal Institute of Technology School of Electrical Engineering and Computer Science Stockholm Sweden

ISBN: (纸本)9798350311990

Quantum computing is emerging as an important (but radical) technology that might take us beyond Moore's law for certain applications. Today, in parallel with improving quantum computers, computer scientists are relying heavily on quantum circuit simulators to develop algorithms. Most existing quantum circuit simulators run on general-purpose CPUs or GPUs. However, at the same time, quantum circuits themselves offer multiple opportunities for parallelization, some of which could map better to other architecture- architectures such as reconfigurable systems. In this early work, we created a quantum circuit simulator system called Q2Logic. Q2Logic is a coarse-grained reconfigurable architecture (CGRA) implemented as an overlay on Field-Programmable Gate Arrays (fpgas), but specialized towards quantum simulations. We described how Q2Logic has been created and reveal implementation details, limitations, and opportunities. We end the study by empirically comparing the performance of Q2Logic (running on a Intel Agilex FPGA) against the state-of-the-art framework SVSim (running on a modern processor), showing improvements in three large circuits(#qbit≥27), where Q2Logic can be up-to 7x faster. © 2023 IEEE.

关键词： Circuit simulation

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A Compilation Toolchain of Neural Networks for FPGA Backend 15

A Compilation Toolchain of Neural Networks for FPGA Backend

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15th IEEE International conference on ASIC, ASICON 2023

作者： Zeng, Jun Wang, Panfeng Wang, Haili Yao, Hailong Sun, Fuchun Tsinghua University Beijing China Hercules Microelectronics Co. Ltd. Beijing China University of Science and Technology Beijing Beijing China

ISBN: (纸本)9798350312980

As neural networks are widely used in embedded and end-device applications, power consumption and performance optimization for specific applications, such as edge computing, are gaining increasing attention. fpgas have been used in embedded neural network applications due to their high parallelism, energy efficiency, reconfigurability, and customizability. However, traditional FPGA programming techniques fail to meet the rapid and iterative development requirements of embedded applications, which also limit the development of fpgas. Researchers have attempted to break through the language-level barriers and implement end-to-end flow. Xilinx's Vitis and LeFlow are proposed to import and execute neural network applications on fpgas. However, existing works are all focused on chips from foreign manufacturers such as Xilinx, and there lacks the support for domestic chips. This paper proposes a complete set of neural network compilation toolchain for domestic FPGA backend, which consist of a developer-friendly Python front-end and a complete FPGA back-end development flow that relieves FPGA developers from the cumbersome hardware programming tasks, and therefore improves the development efficiency of embedded neural network *** main contributions of this paper are listed as follows. (1) We propose a complete FPGA neural network toolchain;(2) We summarize a code specification friendly for high-level synthesis process, and based on this specification we propose a code generation algorithm based on the operator template. Experimental results show that the proposed general compilation toolchain works correctly for adapting the neural network on the backend of domestic FPGA, with a reduction of about 64% of the trigger resources compared with the generated code from the state-of-the-art compilation framework. © 2023 IEEE.

关键词： Code Generation Compilation High-level Synthesis Neural Network Storage Allocation

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A Scalable ARM+FPGA-Based CNN Accelerator with Limited Hardware Resources 42

A Scalable ARM+FPGA-Based CNN Accelerator with Limited Hardw...

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42nd Chinese Control conference, CCC 2023

作者： Ye, Jinlin Zhang, Wei Hebei University of Technology Tianjin300401 China Hebei University of Technology Control Engineering Technology Innovation Center of Hebei Province Tianjin300401 China

ISBN: (纸本)9789887581543

General processors cannot meet the requirements of low power consumption and high performance in mobile application scenarios, the hardware research platform of CNNs has begun to turn to high-performance computing platforms such as GPUs and fpgas. The GPU contains a large number of stream processors to execute operations in parallel, which greatly reduces the operation time of the model. However, because of its large power consumption, mobile applications can hardly afford the GPU's power requirement. Compared with GPUs, fpgas also have parallel architecture, but the power consumption is much lower, which is suitable for CNN mobile application scenarios. In this work, concerning that fpgas with large resource can meet the deployment requirements of CNNs but they are too expensive. How to deploy CNNs with little-resource has become an urgent problem to be solved. Based on this, we propose a scalable ARM+FPGA-based CNN accelerator with limited hardware resources, data flow is controlled through ARM, network is computed through FPGA. LeNet is adopted as the acceleration target, experiments were carried out on MNIST datasets and under the little-resource FPGA xc7z020clg400-2. The result show that at the frequency of 100 MHz, the accuracy of the accelerator prediction of 10000 images is 98.57% and the processing time of each image is 16.09ms. © 2023 Technical Committee on Control Theory, Chinese Association of Automation.

关键词： Mobile computing

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