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检索条件"任意字段=Conference on Reconfigurable Technology - FPGAs for Computing and Applications"

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A Compilation Toolchain of Neural Networks for FPGA Backend 15

A Compilation Toolchain of Neural Networks for FPGA Backend

引用

15th IEEE International conference on ASIC, ASICON 2023

作者： Zeng, Jun Wang, Panfeng Wang, Haili Yao, Hailong Sun, Fuchun Tsinghua University Beijing China Hercules Microelectronics Co. Ltd. Beijing China University of Science and Technology Beijing Beijing China

ISBN: (纸本)9798350312980

As neural networks are widely used in embedded and end-device applications, power consumption and performance optimization for specific applications, such as edge computing, are gaining increasing attention. fpgas have been used in embedded neural network applications due to their high parallelism, energy efficiency, reconfigurability, and customizability. However, traditional FPGA programming techniques fail to meet the rapid and iterative development requirements of embedded applications, which also limit the development of fpgas. Researchers have attempted to break through the language-level barriers and implement end-to-end flow. Xilinx's Vitis and LeFlow are proposed to import and execute neural network applications on fpgas. However, existing works are all focused on chips from foreign manufacturers such as Xilinx, and there lacks the support for domestic chips. This paper proposes a complete set of neural network compilation toolchain for domestic FPGA backend, which consist of a developer-friendly Python front-end and a complete FPGA back-end development flow that relieves FPGA developers from the cumbersome hardware programming tasks, and therefore improves the development efficiency of embedded neural network *** main contributions of this paper are listed as follows. (1) We propose a complete FPGA neural network toolchain;(2) We summarize a code specification friendly for high-level synthesis process, and based on this specification we propose a code generation algorithm based on the operator template. Experimental results show that the proposed general compilation toolchain works correctly for adapting the neural network on the backend of domestic FPGA, with a reduction of about 64% of the trigger resources compared with the generated code from the state-of-the-art compilation framework. © 2023 IEEE.

关键词： Code Generation Compilation High-level Synthesis Neural Network Storage Allocation

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A Scalable ARM+FPGA-Based CNN Accelerator with Limited Hardware Resources 42

A Scalable ARM+FPGA-Based CNN Accelerator with Limited Hardw...

引用

42nd Chinese Control conference, CCC 2023

作者： Ye, Jinlin Zhang, Wei Hebei University of Technology Tianjin300401 China Hebei University of Technology Control Engineering Technology Innovation Center of Hebei Province Tianjin300401 China

ISBN: (纸本)9789887581543

General processors cannot meet the requirements of low power consumption and high performance in mobile application scenarios, the hardware research platform of CNNs has begun to turn to high-performance computing platforms such as GPUs and fpgas. The GPU contains a large number of stream processors to execute operations in parallel, which greatly reduces the operation time of the model. However, because of its large power consumption, mobile applications can hardly afford the GPU's power requirement. Compared with GPUs, fpgas also have parallel architecture, but the power consumption is much lower, which is suitable for CNN mobile application scenarios. In this work, concerning that fpgas with large resource can meet the deployment requirements of CNNs but they are too expensive. How to deploy CNNs with little-resource has become an urgent problem to be solved. Based on this, we propose a scalable ARM+FPGA-based CNN accelerator with limited hardware resources, data flow is controlled through ARM, network is computed through FPGA. LeNet is adopted as the acceleration target, experiments were carried out on MNIST datasets and under the little-resource FPGA xc7z020clg400-2. The result show that at the frequency of 100 MHz, the accuracy of the accelerator prediction of 10000 images is 98.57% and the processing time of each image is 16.09ms. © 2023 Technical Committee on Control Theory, Chinese Association of Automation.

关键词： Mobile computing

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Invited Paper: RapidWright: Unleashing the Full Power of FPGA technology with Domain-Specific Tooling 42

Invited Paper: RapidWright: Unleashing the Full Power of FPG...

引用

42nd IEEE/ACM International conference on Computer-Aided Design (ICCAD)

作者： Lavin, Chris Hung, Eddie Adv Micro Devices Inc AMD Res & Adv Dev Santa Clara CA 95054 USA

ISBN: (纸本)9798350322255

The era of domain-specific computing has created an environment that drives for the best performance possible from silicon and tools. Novel and unique implementation strategies for fpgas that may have been infeasible in the past are now sought after in the search of better performance or faster compile time. The ability to optimize for domain-specific attributes in FPGA implementations is now more important than ever and both industry and research institutions need better ways to fully harness the programmable potential of fpgas. This paper describes RapidWright, an open source framework from AMD Research and Advanced Development, and how it enables design implementation to be customized on commercial FPGA devices. RapidWright enables strategies previously infeasible or impossible to designers and provides sufficient flexibility to leverage domain-specific attributes in their applications for the highest performance, compile-time, or timing closure predictability. We demonstrate how the RapidWright framework has been a fundamental enabling factor in a variety of practical research efforts that have led up to 30% higher quality-of-result (QoR) and compile time improvements of 5x or greater across a number of applications.

关键词： AMD back-end tools FPGA placement Rapid-Wright routing timing closure Vivado Xilinx

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Accelerating PageRank Algorithmic Tasks with a new Programmable Hardware Architecture 9

Accelerating PageRank Algorithmic Tasks with a new Programma...

引用

9th Annual IEEE International conference on Rebooting computing, ICRC 2024

作者： Chowdhury, Md Rownak Hossain Rahman, Mostafizur Division of Energy Matters and Systems University of Missouri-Kansas City (UMKC) Kansas City MO United States

ISBN: (纸本)9798331541279

Addressing the growing demands of artificial intelligence (AI) and data analytics requires new computing approaches. In this paper, we propose a reconfigurable hardware accelerator designed specifically for AI and data-intensive applications. Our architecture features a messaging-based intelligent computing scheme that enables dynamic programming at runtime using a minimal instruction set. To assess our hardware's effectiveness, we conducted a case study using TSMC 28nm technology node. The simulation-based study benchmarks our hardware against the Tensor Processing Unit (TPU) and involves analyzing a protein network using the computationally demanding PageRank algorithm. The results indicate that our hardware can analyze a 5,000-node protein network in just 213.6 milliseconds over 100 iterations. Moreover, our design outperforms systolic array based TPU demonstrating an 11% reduction in latency for matrix vector multiplication. These outcomes signify the potential of our design to achieve cutting-edge performance in next-generation AI applications. © 2024 IEEE.

关键词： Artificial Intelligence Hardware Accelerator PageRank Algorithm Protein Network Analysis reconfigurable computing

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Comparative Analysis of Power, Temperature and Hardware Utilization on Implementation of Half Adder

Comparative Analysis of Power, Temperature and Hardware Util...

引用

2023 International conference on Circuit Power and computing Technologies, ICCPCT 2023

作者： Shrivastava, Shishir Kaur, Amanpreet Chitkara University Institute of Engineering and Technology Chitkara University Punjab India

ISBN: (纸本)9798350333244

Several developing countries have been faced with serious energy deficits. Environmentally conscious communication has been advanced by the creation of an economical half adder using the Vivado software framework and several FPGA families. To determine the most energy-efficient FPGA series, three distinct FPGA families with seven series each were developed: Airtex, Virtex, and Kintex. The Airtex, Virtex, and Kintex families each consume 0.795 watts of power, but the Kintex family consumes 1.013 watts. Temperatures of Airtex, Virtex, and Kintex are 58.5 degrees Celsius, 73.6 degrees Celsius, and 74 degrees Celsius, respectively. Using components from the Airtex-7 series instead of those from the other two families reduces power dissipation, as specified. Airtex's power efficiency is comparable to that of rival FPGA architectures. Using this strategy, it is possible to meet future energy demands. Moreover, Airtex board is more affordable than competing brands. Airtex fpgas have a unique set of characteristics that make them suitable for specific applications when compared to other FPGA families. Using this strategy, future energy demands can be met. Additionally, Airtex board is less expensive than competing brands. Compared to other FPGA families, Airtex fpgas have a unique set of characteristics that make them suitable for specific applications. © 2023 IEEE.

关键词： Field programmable gate arrays (FPGA)

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FPGA-Implemented reconfigurable Logic Locking Using N-Stage Delays for Obfuscation

FPGA-Implemented Reconfigurable Logic Locking Using N-Stage ...

引用

2025 IEEE International Students' conference on Electrical, Electronics and Computer Science, SCEECS 2025

作者： Srivastava, Saurabh Nakhate, Sangeeta Maulana Azad National Institute of Technology Dept. of Ece Bhopal India

ISBN: (纸本)9798331529833

System security is becoming an increasingly essential feature of modern computing systems, particularly programmable hardware such as Field Programmable Gate arrays (FPGA), employed in various applications such as autonomous systems and digital networks. However, safeguarding FPGA-based devices against IP theft and reverse engineering is difficult and a big concern for the semiconductor and defense industries. Previously, various obfuscation approaches such as gate level obfuscation, camouflaging, and strong puff were employed to make a distinct key for every chip. These designs, however, are more area-intensive, consume more power, and are easier to crack the key. In this research, we propose a novel obfuscation idea that integrates a reconfigurable hardware obfuscation block into the original circuit with an additional N-stage Delay circuit to enhance overall system security and resistance to threats. The present idea relates to the increase in the security of the system against the piracy, overbuilding and from the cloning and camouflaging of the chip. The proposed technique does not have any bulky circuit, and it is easily realizable and just requires some additional modules that can easily reconfigured with a very smaller area and power overhead thereby offering performance benefits and increasing the time of sat attack iteration, making the locking system more complex and difficult to decode. © 2025 IEEE.

关键词： Reverse engineering

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ROMA: A reconfigurable On-chip Memory Architecture for Multi-core Accelerators 25

ROMA: A Reconfigurable On-chip Memory Architecture for Multi...

引用

25th IEEE International conferences on High Performance computing and Communications, 9th International conference on Data Science and Systems, 21st IEEE International conference on Smart City and 9th IEEE International conference on Dependability in Sensor, Cloud and Big Data Systems and applications, HPCC/DSS/SmartCity/DependSys 2023

作者： Qin, Shantian Li, Wenming Fan, Zhihua Wang, Zhen Liu, Tianyu Wu, Haibin Zhang, Kunming An, Xuejun Ye, Xiaochun Fan, Dongrui Institute of Computing Technology State Key Lab of Processors Cas Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9798350330014

Designing efficient on-chip memory solutions for multi-core accelerators is essential to mitigating the impact of the memory wall and enhancing their overall performance. Among prevalent on-chip memory solutions, scratchpad memory (SPM) and cache stand out. Unfortunately, both SPM and cache excel only in specific scenarios, lacking broad applicability across various scenarios. In this paper, we propose a reconfigurable On-chip Memory Architecture (ROMA) that combines the benefits of SPM and cache. First, we decouple the prefetchable data access from the application execution and describe an ISA that can support explicit decoupled prefetch and postback. Then, we introduce an on-chip memory microarchitecture for multi-core accelerators, reducing the area overhead by utilizing the reconfigurable physical storage shared by SPM and cache. Finally, we present a mechanism for data mapping and on-chip memory partitioning in an application targeted to ROMA-based architectures, facilitating efficient data classification into prefetchable and non-prefetchable categories. Experimental results show that our method achieves an average access latency decrease of 34.8 % and up to 17.1 % access energy reduction compared with existing on-chip memory architectures across a range of applications. © 2023 IEEE.

关键词： Memory architecture

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A Review on reconfigurable Antenna and its Design Methods for Sub-6 GHz applications

A Review on Reconfigurable Antenna and its Design Methods fo...

引用

2024 International conference on Integrated Circuits, Communication, and computing Systems, ICIC3S 2024

作者： Bhickta, Shalini Jaglan, Naveen Kumar, Amit Jaypee University of Information Technology Department of Electronics and Communication Engineering Solan Waknaghat India Jaypee University of Information Technology Department of Computer Science and Engineering Solan Waknaghat India

ISBN: (纸本)9798350364088

In modern wireless tele- communication, the key element for better and higher performance of the communication system is an Antenna. An antenna which removes all complex issues of weather, scattering and effects of multiple paths is in demand for current wireless system issues. The Antenna with Reconfiguration capabilities in current scenario solves these issues. The popularity of Reconfiguration in antennas has seen a significant growth due to its versatile capabilities. Therefore, reconfiguration in the structure of an Antenna without changing the physical dimensions and saving space realize the goal of high speed, gain, channel capacity and signal-to-Noise Ratios (SNR). In this paper a brief knowledge of various methods of designing a reconfiguration antenna is reviewed. The different switching techniques used for the activating the reconfiguration mechanism is discussed. The advancement of reconfiguration in multi-input multi-output (MIMO) systems is also studied. © 2024 IEEE.

关键词： Signal to noise ratio

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A Double Approximate Neural Hardware Accelerator 29

A Double Approximate Neural Hardware Accelerator

引用

29th International Computer conference, Computer Society of Iran, CSICC 2025

作者： Nazari, Samira Azarpeyvand, Ali Ghasempouri, Tara University of Zanjan Zanjan Iran Tallinn University of Technology Tallinn Estonia

ISBN: (纸本)9798331523114

Emerging as a prominent approach, approximate computing has found widespread application in diverse fields such as data mining and image processing, effectively curbing area and power consumption in processors. One compelling avenue for integrating approximate computing involves the integration of a neural accelerator alongside the primary core, offering a delicate balance between computational efficiency and precision. A Neural Processing Unit (NPU) emulates regions of approximate code using neural networks. In this article, we introduce ANPiler-an innovative framework that augments the existing neural processing unit with a reconfigurable layer of approximation, achieved through the integration of inexact arithmetic building blocks. ANPiler empowers the design of neural accelerators featuring imprecise adders or multipliers, resulting in reductions of about 5.55% in power consumption and approximately 13.09% in area compared to a precise neural processing unit coupled with a main core. These gains are achieved with almost the same accuracy as before, further underpinning energy savings of 3.0× compared to general-purpose processors, thereby reinforcing the value proposition of an exact NPU in practical applications. © 2025 IEEE.

关键词： Digital arithmetic

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A High-Utilization reconfigurable Digital computing-in-Memory SRAM Using Dynamic Logic for Edge Neural Network applications 4th

A High-Utilization Reconfigurable Digital Computing-in-Memor...

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4th International conference on Frontiers of Electronics, Information and Computation Technologies, ICFEICT 2024

作者： Su, Xiangguang Mai, Yangzhan School of Microelectronics Science and Technology Sun Yat-sen University Guangzhou China

ISBN: (纸本)9789819653171

This paper presents a digital computing-in-memory (CIM) SRAM that can effectively execute small to medium size various-bit precision quantized neural networks. This design uses dynamic logic to compute the bitwise multiplication to reduce area overhead and achieve high performance. The design can be reconfigured to support various bit precision multiply-and-accumulate (MAC) operations in a bit serial manner. The bit cell array consists of 32 computing sections and each section has an independent bit sum and accumulate unit in order to make the utilization more efficient when executing small MAC operations. By adopting the foundry provided push rule 8T SRAM bit cell, the design achieves a compact area and high stability. This design is implemented in 40 nm CMOS technology. The simulation result shows that this design achieves a maximum area efficiency of 9985 GOPS/mm2 and a maximum energy efficiency of 122 TOPS/W. Furthermore, taking MobileNet as an example, this design demonstrates much higher utilization compared with other state-of-the-art SRAM CIM macros. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Logic design

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