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2nd International conference on Machine Learning and Autonomous Systems, ICMLAS 2025

作者： Mhatre, Sagar Dongre, Vinitkumar Jayaprakash Mande, Sudhakar K J Somaiya Institute Department of Electronics and Telecommunication Mumbai India Thakur College of Engg.&Tech Department of Electronics and Telecommunication Mumbai India Don Bosco institute of technology Department of Electronics and Telecommunication Mumbai India

ISBN: (纸本)9798331505745

Field-Programmable Gate Arrays (fpgas) provide compelling advantages for accelerating Long Short-Term Memory (LSTM) networks, particularly in edge computing applications where performance and power efficiency are critical. This study presents an optimized FPGA-based LSTM accelerator implemented using High-Level Synthesis (HLS) on the PYNQ Z2 board. The proposed design achieves 3.71x performance improvement over a software-based implementation running on the Processing System (PS) of the PYNQ Z2, reducing execution time significantly. The accelerator efficiently utilizes FPGA resources, with 63% LUT and 61% DSP utilization, ensuring a balanced trade-off between computational throughput and hardware constraints. Power analysis reveals that hardware consumes very small fraction of the total power. This study demonstrates that FPGA-based LSTM accelerators provide significant speedup and energy efficiency, making them an attractive solution for real-time, resource-constrained machine learning applications at edge. © 2025 IEEE.

关键词： Integrated circuit design

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Frequency reconfigurable Antenna and its Switching Techniques for Wireless Communication Systems: A Study 8

Frequency Reconfigurable Antenna and its Switching Technique...

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8th International conference on Advanced computing and Communication Systems, ICACCS 2022

作者： Karthika, K. Kavitha, K. Darsani, S. Preethi, B. Pavithra, P. Sree Kumaraguru College of Technology Department of Ece Coimbatore India Velammal College of Engineering and Technology Department of Ece Madurai India

ISBN: (纸本)9781665408165

In wireless communication, antenna plays a vital role in establishing an effective communication. Number of antennas are needed for various applications. This made the antenna researchers to contribute towards the design of adaptive antennas to perform according to the user's need. These adaptive antennas are also known as reconfigurable antennas. The reconfigurable antennas have the capacity of dynamically resonating in different frequencies, switching its radiation pattern and polarization. This paper explores about the design aspects of frequency reconfigurable antennas via various switching techniques. Hence this paper will help the antenna researchers to explore the various research techniques and scopes to design an effective frequency reconfigurable antenna. © 2022 IEEE.

关键词： Polarization

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reconfigurable Virtual Accelerator (ReVA) for Large-Scale Acceleration Circuits 30th

Reconfigurable Virtual Accelerator (ReVA) for Large-Scale A...

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30th International conference on Parallel and Distributed Processing Techniques, PDPTA 2024, held as part of the World Congress in Computer Science, Computer Engineering and Applied computing, CSCE 2024

作者： Yaguchi, Kazuki Maeda, Eriko Kawai, Shunya Teruya, Daichi Osana, Yasunori Miyoshi, Takefumi Nakajo, Hironori Department of Electrical Engineering and Computer Science Graduate School of Engineering Tokyo University of Agriculture and Technology 2-24-16 Nakacho Tokyo Koganei-shi184-8588 Japan Research and Education Institute for Semiconductors and Informatics Kumamoto University 2-39-1 Kurokami Kumamoto Chuo-ku860-8555 Japan WasaLabo LLC. K-2 Buransyu 6-5-20 Minaminaruse Tokyo Machida-shi194-0045 Japan Division of Advanced Information Technology and Computer Science Institute of Engineering Tokyo University of Agriculture and Technology 2-24-16 Nakacho Tokyo Koganei-shi184-8588 Japan

ISBN: (纸本)9783031856372

In recent years, hardware acceleration in large-scale computing fields such as Artificial Intelligence and High Performance computing, faces hardware resource shortages. To overcome this problem, we propose reconfigurable Virtual Accelerator (ReVA), which allows a large-scale acceleration circuit built using multiple fpgas, processors and memory subsystems, to accelerate application programs. We have designed and implemented a prototype of Virtual Accelerator (VA) Generator for ReVA to investigate its performance. The VA Generator prototype employs an open-source HLS automated split compilation tool, RapidStream, to automatically generate placed-and-routed virtual accelerators that can be implemented on multiple fpgas based on HLS dataflow designs. The VA Generator, which places VAs on the appropriate regions of fpgas, allows large circuits to be performed like a single accelerator using several fpgas. In addition, RapidStream’s parallel compilation technology allows the VA Generator to suppress the increasing compilation time according to the circuit size. Moreover, with our VA Generator prototype we have built and evaluated a VA of a large-scale circuit which cannot be fit in a single FPGA with multiple fpgas. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： reconfigurable hardware

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Supporting Dynamic Control-Flow Execution for Runtime reconfigurable Processors

Supporting Dynamic Control-Flow Execution for Runtime Reconf...

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2023 International conference on Microelectronics, ICM 2023

作者： Nassar, Hassan Youssef, Rafik Bauer, Lars Henkel, Jorg Karlsruhe Institute of Technology Embedded Systems Germany

ISBN: (纸本)9798350380828

As the need for more computing power grows, traditional methods are hitting limits. To boost performance, we're expanding Central Processing Unit (CPU) capabilities and using specialized hardware accelerators. For example, mobile devices usually have cameras, video encoding, and audio accelerators. To perform the different tasks, these accelerators execute microcode programs. These accelerators, however, take up space and often sit idle. reconfigurable processors offer a solution. They have a normal core connected to several accelerator slots. These accelerator slots can be filled during runtime to accommodate the application running. Once one application finishes and another application is running, the accelerators can be switched. For example, playing music after using the camera. In this work, we introduce dynamic control-flow execution for the microcode of runtime reconfigurable processors, i.e., support for loops, conditional jumps, and exception handling. We benchmark using four different applications from four domains (object detection, ocean movement simulation, artificial intelligence and security) that all are compute-intensive and would require the dynamic control-flow when executed on reconfigurable processors. We show that the dynamic control-flow allows different applications to be executed with significant speedup in comparison with execution on general-purpose processors. © 2023 IEEE.

关键词： Cameras

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reconfigurable Framework for Resilient Semantic Segmentation for Space applications

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ACM TRANSACTIONS ON reconfigurable technology AND SYSTEMS 2021年第4期14卷 1-32页

作者： Sabogal, Sebastian George, Alan Crum, Gary Univ Pittsburgh NSF SHREC Ctr Swanson Sch Engn Pittsburgh PA 15213 USA NASA Goddard Space Flight Ctr Sci Data Proc Branch Code 587 Greenbelt MD 20771 USA

Deep learning (DL) presents new opportunities for enabling spacecraft autonomy, onboard analysis, and intelligent applications for space missions. However, DL applications are computationally intensive and often infeasible to deploy on radiation-hardened (rad-hard) processors, which traditionally harness a fraction of the computational capability of their commercial-off-the-shelf counterparts. Commercial fpgas and systemon-chips present numerous architectural advantages and provide the computation capabilities to enable onboard DL applications;however, these devices are highly susceptible to radiation-induced single-event effects (SEEs) that can degrade the dependability of DL applications. In this article, we propose reconfigurable ConvNet (RECON), a reconfigurable acceleration framework for dependable, high-performance semantic segmentation for space applications. In RECON, we propose both selective and adaptive approaches to enable efficient SEE mitigation. In our selective approach, control-flow parts are selectively protected by triple-modular redundancy to minimize SEE-induced hangs, and in our adaptive approach, partial reconfiguration is used to adapt the mitigation of dataflow parts in response to a dynamic radiation environment. Combined, both approaches enable RECON tomaximize system performability subject to mission availability constraints. We perform fault injection and neutron irradiation to observe the susceptibility of RECON and use dependability modeling to evaluate RECON in various orbital case studies to demonstrate a 1.5-3.0x performability improvement in both performance and energy efficiency compared to static approaches.

关键词： Environmentally adaptive computing dependability modeling space computing single-event effects

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Parallel Implementation of SHA256 on Multizone Heterogeneous Systems 21

Parallel Implementation of SHA256 on Multizone Heterogeneous...

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21st IEEE International Symposium on Parallel and Distributed Processing with applications, 13th IEEE International conference on Big Data and Cloud computing, 16th IEEE International conference on Social computing and Networking and 13th International conference on Sustainable computing and Communications, ISPA/BDCloud/SocialCom/SustainCom 2023

作者： Luo, Yongtao Liu, Jie Xiao, Tiaojie Gong, Chunye National University of Defense Technology Science and Technology on Parallel and Distributed Processing Laboratory Laboratory of Digitizing Program for Frontier Equipment Changsha China National Supercomputer Center in Tianjin Tianjin China

ISBN: (纸本)9798350329223

SHA-256 plays an important role in widely used applications, such as data security, data integrity, digital signatures, and cryptocurrencies. However, most of the current optimized implementations of SHA-256 are based on CPUs or dedicated hardware, such as ASICs and fpgas. Consequently, there is a need to explore whether new heterogeneous parallel framework can improve the computational performance of the hash function. To address this issue, we conducted a study on the MT-3000 platform, which is a special architecture processor for the next-generation exascale prototype supercomputer. We proposed MT-SHA256, a heterogeneous multistage parallel implementation for hashing multiple messages on the MT-3000. Combining the architectural features of this processor, we developed an effective solution that significantly improved the computational performance of SHA-256. As a result, MT-SHA256 achieved a maximum throughput of 1045.68 MB/s on a single acceleration core of MT-3000. This is 9.84x higher than the C code implementation on one CPU core of MT-3000. We also performed a scalability test and found that MT-SHA256 achieved a throughput of 98.04 GB/s on a computing node, and extended to 512 nodes (2048 acceleration clusters) on this system with good scalability. © 2023 IEEE.

关键词： Hash functions

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Development of a High-Speed and Accurate Face Recognition System Based on fpgas

Development of a High-Speed and Accurate Face Recognition Sy...

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Proceedings of the International conference on Intelligent Systems and Network, ICISN 2023

作者： Nguyen, Ha Xuan Hoang, Dong Nhu Dang, Tuan Minh Hanoi University of Science and Technology No. 1 Dai Co Viet Hanoi Viet Nam CMC Applied Technology Institute CMC Corporation 11 Duy Tan Hanoi Viet Nam CMC University CMC Corporation 11 Duy Tan Hanoi Viet Nam Posts and Telecommunication Institute of Technology Ha Dong Hanoi Viet Nam

ISBN: (纸本)9789819947249

In this work, a high-speed and accurate face recognition system based on Field Programmable Gate Arrays (fpgas) was completely developed. A complete pipeline that contains a sequence of processing steps, including preprocessing, face feature extraction, and matching, is proposed. For processing steps, lightweight deep neural models were developed and optimized so that they could be computationally accelerated on an FPGA. Besides the core processing pipeline, a database as well as a user application server were also developed to fully meet the requirements of readily commercialized applications. The experimental evaluation results show that our system has a very high accuracy based on the BLUFR benchmark, with a precision of 99.336%. Also, the system is very computationally efficient, as the computing time to recognize an ID in a dataset of 1000 IDs with 4000 images on the FPGA ZCU-104 is only 30.3 ms. For the critical case, the system can process 8 camera streams and simultaneously recognize a maximum of 80 IDs within a computing time of 342.3 ms for each ID. With its high-speed and accuracy characteristics, the developed system has a high potential for practical applications. © 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： Pipelines

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Joint Optimization of Computation and Communication Resources for RIS-Aided Multi-Cell Multi-User Wireless Caching Networks 100

Joint Optimization of Computation and Communication Resource...

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100th IEEE Vehicular technology conference, VTC 2024-Fall

作者： Huang, Yue-Rong Lee, Ming-Chun National Yang Ming Chiao Tung University Institute of Communications Engineering Taiwan

ISBN: (纸本)9798331517786

To facilitate massive multiple-input multiple-output systems and millimeter-wave communications, reconfigurable intelligent surface (RIS) has drawn significant attention. On the other hand, to serve computation- and data-intensive applications, the optimization jointly considering caching, computing, and communication (3C) resources has also been widely discussed. To fill the gap that the optimization considering 3C has not been well-explored in RIS-aided networks, this paper investigates the joint optimization of computation and communication (2C) resources and RIS design in multi-cell multi-user wireless caching networks. Based on the formulated latency minimization problem, we propose a joint 2C and RIS optimization approach. Our approach solves the latency minimization problem by first decomposing it into several subproblems, and then iteratively solving the subproblems until convergence. Computer simulations show that our approach can effectively improve the network performance and outperform the reference schemes. © 2024 IEEE.

关键词： Edge computing

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INVITED PAPER: An Energy-Efficient and reconfigurable DNN Accelerator for Optic-Fiber based Edge Sensing and computing

INVITED PAPER: An Energy-Efficient and Reconfigurable DNN Ac...

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2023 IEEE International conference on Integrated Circuits, Technologies and applications, ICTA 2023

作者： Duan, Ziang Ma, Ruohan Shen, Zixuan Ge, Zhao Wu, Hao Tang, Ming Wang, Chao School of Optical and Electronic Information Huazhong University of Science and Technology Wuhan China School of Integrated Circuits Huazhong University of Science and Technology Wuhan China Wuhan National Laboratory for Optoelectronics Wuhan China

ISBN: (纸本)9798350344288

The signals of distributed optic-fiber may represent information related to certain events which can be classified by Deep Neural Networks (DNN). However, energy-efficient and real-time classification with different DNNs for different edge applications is a great challenge. This paper proposes a reconfigurable hardware accelerator design for DNNs with different structures to classify the signals from various optic-fiber sensors efficiently in real time. By exploiting the arithmetic operation similarity, the proposed reconfigurable design reuses a PE array to implement different convolutional layers and network structures of DNNs, and also utilizes sparsity in DNNs to achieve high energy efficiency and low computation latency. In addition, a design space exploration method is proposed to reach an optimal balance between mitigating on-chip memory overhead and minimizing computation latency so as to effectively achieve low latency and power consumption. FPGA implementation shows that it can achieve a reconfigurable design with 26484 LUTs and 14366 FFs. It outperforms the CPU/GPU solution, i.e., 137 and 99 times in energy efficiency at 180 MHz, respectively. A preliminary Python simulation results in a case study shows that the accuracy of Resnet-12 implemented by the proposed design is 98.94% on the optic-fiber vibration signal classification task. © 2023 IEEE.

关键词： Deep neural networks

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Proposed Edge computing Neural Accelerator 4

Proposed Edge Computing Neural Accelerator

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4th IEEE International conference on ICT in Business Industry and Government, ICTBIG 2024

作者： Singh, Vikram Aditya Verma, Rajesh Saini, Dori Singh Berwal, Krishan Vishwakarna, Sanotsh Kr Military College of Telecommunication Engineering Faculty of Telecommunication Engineering Indore India Computer Discount Warehouse Indore India Indian Institute of Technology Indore India

ISBN: (纸本)9798331518981

Edge computing is revolutionizing data processing, especially for applications like surveillance and traffic control systems. The data being processed closer to the source (e.g., cameras or sensors), with this edge computing reduces communication latency, bandwidth consumption, and power usage, addressing limitations of centralized cloud systems. The integration of machine learning (ML) in edge environments enhances surveillance systems, enabling real-time analytics, such as object detection and activity recognition. Convolutional Neural Networks (CNNs), widely used in video analytics, facilitate instant object recognition at the edge. However, the computational demands of deep neural networks (DNNs) require hardware accelerators like DNN accelerators for efficient deployment. These accelerators, implemented using technologies like Field-Programmable Gate Arrays (fpgas) and Application-Specific Integrated Circuits (ASICs), improve latency and energy efficiency. Key benefits include parallelism, optimized memory management, and energy-efficient processing, essential for resource-constrained environments like surveillance drones. This paper explores the architecture of deep learning accelerators, such as the Edge computing Neural Accelerator (ECNA), focusing on their role in real-time surveillance systems. By leveraging binary-weight convolutional layers and systolic array designs, ECNA significantly enhances processing speed and energy efficiency, enabling real-time video analytics while consuming minimal power. © 2024 IEEE.

关键词： Systolic arrays

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