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检索条件"任意字段=Conference on Reconfigurable Technology - FPGAs for Computing and Applications"

共 2977 条记录，以下是131-140 订阅

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Joint Undervolting and Overclocking Power Scaling Approximation on fpgas 11

Joint Undervolting and Overclocking Power Scaling Approximat...

引用

11th Sensor Signal Processing for Defence conference (SSPD)

作者： Wu, Yun Mota, Joao F. C. Wallace, Andrew M. Heriot Watt Univ Sch Engn & Phys Sci Edinburgh Midlothian Scotland

ISBN: (数字)9781665483483

ISBN: (纸本)9781665483483

For applications in signal processing, Field Programmable Gate Arrays (fpgas) are more flexible than Application Specific Integrated Circuits (ASICs), yet reconfigurable and still power and energy efficient to a degree. Undervolting and overclocking are approximate computing techniques that can further save power and energy, closing the efficiency gap by reducing the static/dynamic power and potentially speeding up the computation. However, these techniques may introduce bit level faults, which affect not only the computational correctness but also the security of the hardware. Understanding these fault behaviors provides necessary information for approximate implementation in low-power and secure design. In this work, we investigate joint undervolting and overclocking of AXI peripherals, specifically on-chip AXI memory access, using different commercial Xilinx Ultrascale+ heterogeneous MPSoCs with practical data movement between the ARM processor and the FPGA. Through experimental study we have observed fine-grained bit-flipping patterns when the voltage and clock are tuned beyond certain thresholds. By judging the probability of bit-flipping in terms of bit error rate, we propose a guideline for a balanced choice of voltage and frequency.

关键词： Approximate computing FPGA Undervolting Overclock

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RMP-MEM: A HW/SW reconfigurable Multi-Port Memory Architecture for Multi-PEA Oriented CGRA 60

RMP-MEM: A HW/SW Reconfigurable Multi-Port Memory Architectu...

引用

60th ACM/IEEE Design Automation conference (DAC)

作者： Wu, Qidie Gu, Jiangyuan Lin, Youxu Han, Boxiao He, Hongjun Hu, Yang Liu, Leibo Wei, Shaojun Yin, Shouyi Tsinghua Univ Sch Integrated Circuits BNRist Beijing 100084 Peoples R China China Mobile Res Inst Beijing 100053 Peoples R China

ISBN: (纸本)9798350323481

Coarse-Grained reconfigurable Architecture (CGRA), especially the one with multiple parallelized Processing Element Arrays (PEA), possesses flexible programmability and high parallel computational efficiency, which relies upon an efficient memory architecture to deliver the corresponding computing power. Multi-PEA oriented CGRA allows for mapping various applications and thus demands a flexible memory to adapt to the ever-changing workloads, whose parallel access also requires an efficient multi-port memory. However, the existing memory designs for CGRA are hard to satisfy those requirements since conventional rigid memories fail to provide the desired flexibility due to fixed structure, and traditional multi-port designs are impractical due to large overhead. Therefore, this paper proposes a hardware/software (HW/SW) hybrid reconfigurable multi-port memory architecture (RMP-MEM) with an instructive analysis for the multi-PEA oriented CGRA. RMP-MEM supports adaptive memory partition and programmer-defined access modes to adapt the different features of memory accesses. Also, RMP-MEM achieves an efficient multi-port implementation by a partially shared mechanism. Furthermore, the microarchitecture of RMP-MEM is optimized multi-directionally, resulting in a significant performance gain. The experimental results indicate that RMP-MEM reduces the parallel access latency by 81.1% and exhibits 28.3% energy efficiency improvement compared to prior designs.

关键词： CGRA Multi-PEA Oriented HW/SW Hybrid reconfigurable Multi-Port Memory

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2024 IEEE International conference on Integrated Circuits, Technologies and applications, ICTA 2024

2024 IEEE International Conference on Integrated Circuits, T...

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2024 IEEE International conference on Integrated Circuits, Technologies and applications, ICTA 2024

ISBN: (纸本)9798331530709

The proceedings contain 114 papers. The topics discussed include: a wide-load-range high-PSR capless low-dropout regulator with adaptive supply-ripple cancellation;an FVF-LDO with differential EA and push-pull super source follower for fast transient response;a 154 FPS efficient single-frame bundle adjustment accelerator for high frame rate mobile robots;an energy-efficient logarithmic-posit-based IN-SRAM computing for neural network acceleration;an index-free coding compression mechanism for vision transformers;heart rate monitoring using FMCW radar with dilated convolutions and residual blocks;a 22nm variation-tolerant clock duty-cycle controller for mitigating aging-induced clock duty-cycle distortion with path replica;a fast-settling hybrid adaptive on-off-delay compensation for series-series wireless power receivers;and reconfigurable buck-boost converter with stacked resonant technology for dual-polarity thermoelectric and photovoltaic energy harvesting.

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33.7 An Adhesive Interposer-Based reconfigurable Multi-Sensor Patch Interface with On-Chip Application Tunable Time-Domain Feature Extraction

33.7 An Adhesive Interposer-Based Reconfigurable Multi-Senso...

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2024 IEEE International Solid-State Circuits conference, ISSCC 2024

作者： Cho, Jeonghoon Pyeon, You Jang Yeom, Junyeong Kim, Hyunjoong Cho, Sanghyeon Kim, Yonggi Kim, Taejung Kwak, Jong-Hyun Choi, Geonjun Lee, Yoonsik Shin, Heungjoo Jeong, Hoon Eui Kim, Jae Joon Ulsan National Institute of Science and Technology Ulsan Korea Republic of

ISBN: (纸本)9798350306200

Heterogeneous multi-sensor patch devices should meet the requirements of various applications, and an adhesive interposer-based patch concept with integrated microscale structures is proposed to provide comfortable pressure-based reconfiguration capability where different kinds of sensor components are easily attached or detached for application-specific purposes. Furthermore, for embedding real-time edge-computing capability into a miniaturized patch device with a conventional legacy microcontroller, a multi-sensor patch interface IC is designed to include on-chip analog feature-extraction and classification engines, supporting various sensor interfaces in environmental and healthcare application. Based on the capacitor-based analog convolutional neural network for voice activity detection [1], a two-step analog feature-extraction scheme of quantized time-domain convolutional neural network (QTD-CNN) and one-shot computing analog binarized neural network (BNN) are proposed to minimize the leakage problem of analog capacitor-based methods through 1b quantization of past data without accuracy degradation, enhancing the overall computation speed. It provides flexible time window control and analog normalization capabilities to support feature extractions and classifications in environmental and healthcare applications. The designed interface IC includes five kinds of readout front-ends for chemo-resistive sensors, electro-chemical sensors, bio-potentials (ExG), photoplethysmogram (PPG), and bio-impedance (BioZ), where every path is designed to provide both wide dynamic range (DR) and compensation capability of gain and offset. A prototype of adhesive interposer-based reconfigurable patch interface is manufactured, and its real-time heterogeneous feature extractions of gas event and arrhythmia detections are experimentally demonstrated. © 2024 IEEE.

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Defective Microstrip Structure Based Phase Shifter with Reduced Size for Phased Antenna Array applications 12

Defective Microstrip Structure Based Phase Shifter with Redu...

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12th IEEE International conference on Intelligent Data Acquisition and Advanced computing Systems: technology and applications, IDAACS 2023

作者： Khan, Hajra Khan, Shahid Nasir, Jamal Ali Shah, Syed Ahson Dalarsson, Mariana Alibakhshikenari, Mohammad Comsats University Islamabad Department of Electrical and Computer Engineering Pakistan Hanyang University Applied Bioelectronics Laboratory Seoul Korea Republic of School of Electrical Engineering and Computer Science Kth Royal Institute of Technology Stockholm Sweden Universidad Carlos Iii de Madrid Department of Signal Theory and Communications Spain

ISBN: (纸本)9798350358056

In this work, we propose a small-size and low-cost phase shifter based on defective microstrip structure (DMS) technique, with a modified reconfigurable unit cell (MRDMS) for WLAN applications at 5.2 GHz. The phase shifter is made up of an MRDMS unit, created by etching slots on a simple microstrip line with an outline of three bridges. To further increase the phase shift, a T-shaped slot is introduced in the central bridge and PIN diodes on the edges of the outer bridges are used. By switching the diodes on and off, the MRDMS unit cell is capable of operating in a variety of different modes to give a phase shift of 37.71° at 5.2 GHz. Additionally, MRDMS unit cells are cascaded for higher phase shift as required. Cascaded two- and four-cell phase shifters were designed and simulated in HFSS and a parametric study on various parameters was conducted to show the detailed operating properties of the proposed phase shifter. Compared to previously reported research, the present study shows that two cascaded phase shifters introduce 75.08° phase shifts and 151.75°, respectively. To the best of our knowledge, this is the maximum phase shift obtained by a phase shifter based on MRDMS. © 2023 IEEE.

关键词： defected microstrip structure phase shifter reconfigurable microwave system

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Towards Automated FPGA Compilation of Spiking Neural Networks

Towards Automated FPGA Compilation of Spiking Neural Network...

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IEEE International conference on Artificial Intelligence Circuits and Systems (AICAS)

作者： Ayan Shymyrbay Mohammed E. Fouda Ahmed Eltawil Department of ECE CEMSE Division King Abdullah University of Science and Technology Thuwal Saudi Arabia Rain Neuromorphics Inc. San Francisco CA USA

ISBN: (数字)9798350383638

ISBN: (纸本)9798350383645

Edge computing and the Internet of Things (IoT) have created a growing demand for low-cost and low-power field programmable gate arrays (fpgas) to facilitate rapid and efficient processing. At the same time, spiking neural networks (SNNs) have gained popularity for their capacity to replicate biological processes and efficiently handle temporal data, making them a favorable choice in various IoT applications. However, designers must possess a comprehensive knowledge of FPGA architecture and programming methodologies to fully exploit the potential of fpgas for SNN implementations. In this work, we propose SpiComp framework aiming to automate the implementation of SNNs on fpgas, leveraging their reconfigurable nature and high efficiency without requiring domain expertise. Results show that the SNN implementations produced by the framework achieve high throughput and have a small energy footprint compared to other implementations in the literature while providing design automation.

关键词： Design automation Circuits and systems Spiking neural networks Computer architecture Logic gates Programming Throughput

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reconfigurable Network Slicing Orchestration in Network Function Virtualization Compatible Operational technology Environment

Reconfigurable Network Slicing Orchestration in Network Func...

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2024 International conference on Communications Control and computing Technologies for Smart Grids

作者： Delgado, Brian G. Kodiles Aguayo, Jared M. Rivera, Abel O. Gomez Tosh, Deepak K. Univ Texas El Paso Dept Comp Sci El Paso TX 79968 USA Johns Hopkins Univ Appl Phys Lab Laurel MD USA Sandia Natl Labs Albuquerque NM USA

ISBN: (纸本)9798350318562;9798350318555

The ongoing transition to Industry 4.0, which is characterized by increased inter-connectivity of cyber-physical systems, requires having time-sensitive, high throughput, and secure transfer of critical data in industrial sites. In this context, network slicing emerges as a critical tool to ensure timely data delivery by provisioning the network resources to cater to specific applications' requirements and mitigating potential cyber attacks. To address these challenges, this paper aims to tackle two key questions essential for the successful implementation of network slicing in industrial environments. First, it investigates architectural considerations for developing a network infrastructure capable of supporting network slicing functionalities effectively. The proposed approach significantly improves deployment efficiency over traditional manual configurations. Second, it delves into the automated orchestration process, elucidating the steps and components involved in transitioning from a static network management approach to dynamically leverage network function virtualization schemes for creating network slices in ad-hoc manner. The system demonstrates high throughput suitable for production-level solutions and maintains exceptionally low latency, making it ideal for ultra-reliable low-latency communications. Even with increased network demands, the system remains stable, with effective Quality of Service (QoS) management, ensuring reliable performance under varying conditions. The proposed architecture outlines the necessary components, services, and communication protocols required for a production-level orchestrator for network segmentation in SCADA environments.

关键词： Cyber-Physical Systems Network Function Virtualization Operational technology Software-Defined Network

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An Energy-efficient and Dual-mode AI Accelerator for Wearable Lung Sound Monitoring

An Energy-efficient and Dual-mode AI Accelerator for Wearabl...

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2024 Biomedical Circuits and Systems conference

作者： Yang, Keyi Liu, Bingqiang Huang, Zirui Ping, Heng Wen, Ziyuan Shen, Zixuan Huang, Chengjun Wang, Chao Huazhong Univ Sci & Technol Sch Opt & Elect Informat Wuhan Peoples R China Huazhong Univ Sci & Technol Sch Integrated Circuits Wuhan Peoples R China Chinese Acad Sci Inst Microelect Beijing Peoples R China

ISBN: (纸本)9798350354966;9798350354959

Lung diseases seriously impact human health. Using Deep Neural Networks (DNNs) to pre-diagnose lung diseases based on lung sounds is a growing trend. However, most existing DNN hardware accelerators perform direct fine-grained multi-category classification for lung sounds, leading to low energy efficiency, as most lung sounds are normal, and only a coarse-grained classification for abnormal detection is sufficient for pre-screening. This paper proposes an energy-efficient Artificial Intelligence (AI) accelerator based on a tightly Two-Stage Hybrid Neural Network (TS-HNN) model for wearable lung-sound monitoring applications. First, a Two-Stage Data Buffering Scheme (TS-DBS) with a custom Local Memory Bank (LMB) is proposed to support the two-stage acceleration of the TS-HNN model. Second, by observing the channel correlation of two major convolution operators, a reconfigurable Processing Element Array (RPEA) is designed for efficiently computing standard/pointwise convolution and depthwise convolution, enhancing the computation efficiency and energy efficiency. The FPGA experimental results show that the proposed AI accelerator can achieve an energy efficiency of 96.97 GOPs/W, and it only consumes 0.39 mJ/frame for normal lung sounds and 2.03 mJ/frame for abnormal lung sounds, which indicates energy efficiency improvement against the state-of-the-art design by 13.41x and 2.58x, respectively.

关键词： Lung Sound Two-Stage Hybrid Neural Network Energy-efficient AI Accelerator Dual-Mode Dataflow reconfigurable Processing Element Array

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Wireless versus Wired Network-on-Chip to Enable the Multi-Tenant Multi-fpgas in Cloud

Wireless versus Wired Network-on-Chip to Enable the Multi-Te...

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IEEE International IOT, Electronics and Mechatronics conference (IEMTRONICS)

作者： Ijaz, Qaiser Bourennane, El-Bay Univ Burgundy ImViA Lab F-21000 Dijon France

ISBN: (纸本)9781665440677

The new era of computing is not CPU-centric but enriched with all the heterogeneous computing resources including the reconfigurable fabric. In multi-FPGA architecture, either deployed within a data center or as a standalone model, inter-FPGA communication is crucial. Network-on-chip exhibits a promising performance for the integration of one FPGA. A sustainable communication architecture requires stable performance as the number of applications or users grows. Wireless network-on-chip has the potential to be that communication architecture, as it boasts the same performance capability as wired solutions in addition to its multicast capacities. We conducted an exploratory study to investigate different performance parameters using the Noxim simulator. The preliminary results showed better average delay and network throughput for wireless network-on-chip as compared to the wired counterpart.

关键词： Wireless NoC multi-fpgas reconfigurable computing

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Design For Agility: A Modular reconfigurable Platform for Heterogeneous Many-Core Architectures 31

Design For Agility: A Modular Reconfigurable Platform for He...

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31st International conference on Field-Programmable Logic and applications (FPL)

作者： Kamaleldin, Ahmed Goehringer, Diana Tech Univ Dresden Chair Adapt Dynam Syst Dresden Germany

ISBN: (纸本)9781665437592

reconfigurable many-core computing platforms are gaining increasing attention for cloud and edge computing because of their high degree of scalability as well as flexibility. Heterogeneous many-core architectures provide more computing capabilities for domain-specific and general-purpose applications. However, bringing heterogeneous and custom computing elements together increases on-chip communication and run-time management complexities. This leads to growing design time and development cost, in addition to lack of platform re-usability. The scope of this PhD work is the design of a modifiable and modular hardware platform that provides a high degree of agility to change types or specifications of computing elements at design and run-time to achieve the best performance for different application demands using the same platform components. Different acceleration strategies and memory hierarchies are supported. In this paper, the proposed platform, preliminary results, and evaluation are presented targeting fpgas. Finally, planned and future works are highlighted.

关键词： reconfigurable computing many-core architecture field programmable gate arrays (FPGA)

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