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检索条件"任意字段=Conference on Reconfigurable Technology - FPGAs for Computing and Applications"

共 2977 条记录，以下是141-150 订阅

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Demonstrating InflatableMod: Untethered and reconfigurable Inflatable Modules for Tabletop-sized Pneumatic Physical Interfaces

Demonstrating InflatableMod: Untethered and Reconfigurable I...

引用

Extended Abstracts of the 2023 CHI conference on Human Factors in computing Systems, CHI EA 2023

作者： Morita, Takafumi Jiang, Ziyuan Aoyama, Kanon Minaminosono, Ayato Kuwajima, Yu Hosoya, Naoki Maeda, Shingo Kakehi, Yasuaki The University of Tokyo Tokyo Japan Shibaura Institute of Technology Tokyo Japan Tokyo Institute of Technology Tokyo Japan

ISBN: (纸本)9781450394222

Inflatable systems have been attracting attention in the field of interaction design. Conventional tabletop-sized pneumatic systems tend to be complex because they require bulky and noisy equipment. Therefore, several liquid-to-gas phase change actuators that use vaporization have been proposed. But these actuators have problems with controllability, reusability, and reconfigurability. In this study, we propose InflatableMod, novel inflatable modules based on the efficient control of liquid-to-gas phase change actuators. These are designed with a compact circuit that has a liquid transfer function to feed the required amount of low-boiling-point liquid into the pouch and a heating function to inflate the pouch by the volume change. This approach allows for a compact, silent, and untethered inflatable system. It is also possible to create an untethered and reconfigurable multi-inflatable system because each module is synchronized. In this paper, we demonstrate the basic operation and some applications with InflatableMod. © 2023 Owner/Author.

关键词： Pneumatics

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FLOWER: A Comprehensive Dataflow Compiler for High-Level Synthesis 20

FLOWER: A Comprehensive Dataflow Compiler for High-Level Syn...

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20th International conference on Field-Programmable technology (ICFPT)

作者： Amiri, Puya Perard-Gayot, Arsene Membarth, Richard Slusallek, Philipp Leissa, Roland Hack, Sebastian German Res Ctr Artificial Intelligence DFKI Bremen Germany TH Ingolstadt THI Res Inst AImot Bavaria Ingolstadt Germany Univ Mannheim Sch Business Informat & Math WIM Mannheim Germany Saarland Univ UdS Saarbrucken Germany

ISBN: (纸本)9781665420105

fpgas have found their way into data centers as accelerator cards, making reconfigurable computing more accessible for high-performance applications. At the same time, new high-level synthesis compilers like Xilinx Vitis and runtime libraries such as XRT attract software programmers into the reconfigurable domain. While software programmers are familiar with task-level and data-parallel programming, fpgas often require different types of parallelism. For example, data-driven parallelism is mandatory to obtain satisfactory hardware designs for pipelined dataflow architectures. However, software programmers are often not acquainted with dataflow architectures-resulting in poor hardware designs. In this work we present FLOWER, a comprehensive compiler infrastructure that provides automatic canonical transformations for high-level synthesis from a domain-specific library. This allows programmers to focus on algorithm implementations rather than low-level optimizations for dataflow architectures. We show that FLOWER allows to synthesize efficient implementations for high-performance streaming applications targeting Systemon-Chip and FPGA accelerator cards, in the context of image processing and computer vision.

关键词： high-level synthesis dataflow compiler FPGA transformations high-performance computing

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A Case for Function-as-a-Service with Disaggregated fpgas 14

A Case for Function-as-a-Service with Disaggregated FPGAs

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IEEE 14th International conference on Cloud computing (CLOUD)

作者： Ringlein, Burkhard Abel, Francois Diamantopoulos, Dionysios Weiss, Beat Hagleitner, Christoph Reichenbach, Marc Fey, Dietmar IBM Res Europe Dublin Ireland Friedrich Alexander Univ Erlangen Nurnberg Erlangen Germany

ISBN: (纸本)9781665400602

The slowdown of Moore's law and the end of Dennard scaling created a demand for specialized accelerators, including Field Programmable Gate Arrays (fpgas), in cloud data centers. Al the same time, compute resources are increasingly consumed via public and private clouds and traditional applications are modernized using scalable microservices and Function-as-a-Service (FaaS) offerings. Nonetheless, true FaaS based on fpgas or other accelerators is virtually absent from the offering catalogs of all major cloud providers. In addition, FPGA applications are typically coded in a monolithic fashion, due to device and vendor specific dependencies, which reduces the portability and usability of FPGA cloud offerings further. However, FPGA-based FaaS can improve execution efficiency and minimize (tail-) latencies while decreasing costs. We propose a novel system architecture, called Mantle, that uses disaggregated fpgas to enable scalable, usable, portable and efficient FaaS offerings for fpgas. Our experimental results demonstrate a significant reduction of end-to-end service provisioning lime to below 7 seconds and an increase in execution efficiency by a factor of 4 with negligible overhead.

关键词： cloud computing reconfigurable computing disaggregated fpgas Shell Role architecture partial reconfiguration FaaS forward compatibility dynamic ISA extensions

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FPGA Based Hardware Accelerator for Bio-Informatics applications

FPGA Based Hardware Accelerator for Bio-Informatics Applicat...

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Innovation in technology (ASIANCON), Asian conference on

作者： Akash Kate Deepti Khurge Electronics and Telecommunication Engineering Pimpri-Chinchwad College of Engineering Pune India

We present the design and implementation of an FPGA-based accelerator for bioinformatics applications in this paper. To process large amounts of data generated by next generation sequencing (NGS) technologies, bioinformatics applications require high-performance computing capabilities. Because of their parallel processing capabilities and reconfigurable hardware, fpgas are a promising solution for accelerating bioinformatics applications. To achieve high throughput and low latency, the proposed accelerator architecture employs parallelism and pipelining. The FPGA accelerator's performance is compared to software implementations on a CPU. The results of the experiments show that the FPGA accelerator outperforms the CPU implementation.

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A Runtime reconfigurable Exact-Approximate Full-Adder Design 6

A Runtime Reconfigurable Exact-Approximate Full-Adder Design

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6th Iranian International conference on Microelectronics, IICM 2024

作者： Naseri, Keihan Jahanirad, Hadi University of Kurdistan Department of Electronics and Communication Engineering Sanandaj Iran

ISBN: (纸本)9798331511371

Approximate arithmetic modules are attractive solutions to save power consumption in error-resilient applications. The full adder (FA), as the core computing module, contributes a major part of arithmetic modules in digital systems. However, designing the FA module to be applied in both approximate and exact modes has become a major goal in low-power integrated circuit design. In this paper, we present a new configurable FA with runtime configurability between exact and approximate modes at the transistor level. The configurability of the proposed FA is achieved using embedded switches in the internal nodes of the circuit. Our circuit provides an output accuracy of 6 in approximate mode. We implemented our adder using GPDK 45-nm technology node and evaluated it with Cadence Virtuoso. Our proposed adder consumes 23 % less power compared to the Mirror Adder when operating in approximate mode. © 2024 IEEE.

关键词： Adders

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Scaling Deep-Learning Pneumonia Detection Inference on a reconfigurable Self-Contained Hardware Platform 6

Scaling Deep-Learning Pneumonia Detection Inference on a Rec...

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6th International conference on Electronics technology, ICET 2023

作者： Wang, Jiangkun Dang, Khanh N. Abdallah, Abderazek Ben The University of Aizu Graduate School of Computer Science and Engineering Fukushima Aizu-Wakamatsu965-8580 Japan

ISBN: (纸本)9798350337693

Artificial Intelligence (AI) has been used in applications to alleviate specific problems in academia and industry. For instance, in healthcare, where edge-based computing platforms are heavily used, when it comes to latency and security issues, the increased demands of application of AI applications such as deep learning require a specific platform to meet the latency, security, and power consumption challenges. This work presents methods and architectures for scaling deep learning inference for pneumonia detection in chest X-ray images based on a reconfigurable self-contained hardware platform named AIRBiS1. The performance evaluation results show that the proposed approach achieves 95.2% detection accuracy of pneumonia over the collected test data with the computer-aided diagnosis scenario. The secure collaborative-learning approach achieves comparable accuracy to the conventional training scenario. However, for rapid batch detection, the detection could be accelerated by 0.023s. Moreover, the system inference acceleration is 13 times (on average) more energy-efficient than conventional approaches.1AIRBiS project, the University of Aizu: https://***/misc/benablab/*** © 2023 IEEE.

关键词： Computer aided diagnosis

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On-chip reconfigurable mode converter by rectangle Sb2S3 inlaid in 4H-SiC 7

On-chip reconfigurable mode converter by rectangle Sb2S3 inl...

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7th Global Intelligent Industry conference, GIIC 2024

作者： Zhu, Danfeng Liao, Zening Chen, Junbo Qiu, Shaobin Deng, Dingnan Ye, Han Meizhou Intelligent Photoelectric Detection Application Engineering Technology Research Center School of Physics and Electrical Engineering Jiaying University Meizhou514015 China State Key Laboratory of Information Photonics and Optical Communications Beijing University of Posts and Telecommunications Beijing100876 China

ISBN: (纸本)9781510682986

Antimony sesquisulfide Sb2S3, an emerging low-loss phase change material, has attracted great interest for its unique properties, enabling its huge potential applications in programmable integrated optics. A reconfigurable mode converter is proposed and demonstrated numerically assisted by a rectangle Sb2S3 inlaid in a slab 4H-SiC waveguide. A three-dimension finite-difference time-domain (3D FDTD) method is employed to simulate and optimize the proposed structure. The TM0-to-TM1 mode conversion is realized with transmittances (T) of 0.91 and mode purity (MP) of 93% at the wavelength of 1550 nm in the crystalline Sb2S3 state. When the Sb2S3 is switched to the amorphous state, the mode-conversion effect disappears, and the incident TM0 mode propagates unimpededly with T > 0.99 and MP > 97.64% within the waveband from 1500 nm to 1600 nm. The nonvolatile reconfigurable mode converter can contribute to programmable photonic integrated circuits and neuromorphic optical computing. © 2024 SPIE.

关键词： Photonic integrated circuits

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An Efficient Computational Performance Analysis Method for CGRA-based Deep Learning Accelerator 2

An Efficient Computational Performance Analysis Method for C...

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2nd Asia conference on Advanced Robotics, Automation, and Control Engineering, ARACE 2023

作者： Liu, Weiheng Chen, Xucan Intelligent Game and Decision Lab BeiJing China

ISBN: (纸本)9798350328363

With the rapid advancement of deep learning technology and the Internet of Things (IoT), new applications are continuously emerging, such as image classification and object tracking, which require deployment on edge computing devices. These applications pose higher demands on computational complexity, latency sensitivity, and rapid iterative updates, while also challenging the energy efficiency and flexibility of edge computing devices. In previous research, we have observed that Coarse-Grained reconfigurable Architecture (CGRA) maintains flexibility post-fabrication and achieves energy efficiency ratios close to ASICs, making it suitable for designing low-power, high-performance edge computing chips. As a result, research on CGRA-based deep learning accelerators has been steadily increasing. To rapidly assess the performance bottlenecks of CGRA in accelerating compute-intensive regions of deep learning applications and provide guidance for specific hardware designs before undertaking CGRA design, we propose a CGRA-based theoretical analysis method. This method enables quick evaluation of CGRA's computational performance under deep learning workloads. Through experimentation, we have demonstrated that our theoretical analysis method is effective and can be used to guide CGRA-based accelerator designs. © 2023 IEEE.

关键词： Edge computing

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HiPReP: High-Performance reconfigurable Processor - Architecture and Compiler 31

HiPReP: High-Performance Reconfigurable Processor - Architec...

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31st International conference on Field-Programmable Logic and applications (FPL)

作者： Kasgen, Philipp Messelka, Mohamed Weinhardt, Markus Osnabruck Univ Appl Sci Fac Engn & Comp Sci Osnabruck Germany

ISBN: (纸本)9781665437592

The computational parallelism and energy efficiency inherent in reconfigurable hardware architectures like finegrained Field-Programmable Gate Arrays (fpgas) and Coarse-Grained reconfigurable Arrays (CGRAs) have been a subject of research mostly for Multimedia applications for many years [1]. The said strengths of reconfigurable systems are also beneficial for other application domains, e.g. High-Performance computing (HPC), since single-core and multicore systems may soon hit scaling limits.

关键词： Multicore processing Computer architecture Parallel processing Hardware Energy efficiency Computational efficiency Field programmable gate arrays

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reconfigurable Stochastic computing Architecture for Computationally Intensive applications 19

Reconfigurable Stochastic Computing Architecture for Computa...

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19th International SoC Design conference (ISOCC) - SoC technology Towards a New Era of Innovation

作者： Kim, Jeongeun Jeong, Yue Ri Cho, Kwonneung Jeong, Won Sik Lee, Seung Eun Seoul Natl Univ Sci & Technol Dept Elect Engn Seoul South Korea

ISBN: (纸本)9781665459716

The design of computation-intensive and complicated applications is limited by hardware resources. To realize efficient utilization of circuit area with lightweight computational logics and execute optimized operation, we propose an architecture of reconfigurable stochastic computing (SC) unit. The proposed SC unit decodes mathematical formula and reconfigures SC circuits to improve design productivity. Compared to the deterministic implementation, the proposed architecture reduces the circuit area by 39.7%.

关键词： Stochastic computing reconfigurable Area efficient

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