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检索条件"任意字段=Conference on Reconfigurable Technology - FPGAs for Computing and Applications"

共 2962 条记录，以下是151-160 订阅

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A Design of SIW-Cavity reconfigurable Antenna for MIMO Wireless Communication applications

A Design of SIW-Cavity Reconfigurable Antenna for MIMO Wirel...

引用

2023 RIVF International conference on computing and Communication Technologies, RIVF 2023

作者： Nguyen, Truong Khang Pham, Kien T. Bui, Cong Danh Kieu Nguyen, Thi Thanh Ninh Dao, Tran Khanh Nguyen, Tuan Duc School of Technology Van Lang University Faculty of Information Technology Ho Chi Minh City Viet Nam School of Electrical Engineering International University Vietnam National University Ho Chi Minh City Viet Nam CONNECT Center School of Engineering Trinity College Dublin Dublin Ireland Binh Thuan College Faculty of Engineering Binh Thuan Viet Nam Ton Duc Thang University Faculty of Electrical and Electronics Engineering Ho Chi Minh City Viet Nam

ISBN: (纸本)9798350315844

In this paper, a 2-by-1 MIMO reconfigurable antenna using Quarter Mode Substrate Integrated Waveguide (QMSIW) is introduced for wireless communication application. By combining three antenna techniques, the proposed design has a compact size due to QMSIW cavity, operation frequency flexibility by using varactor diodes, and channel capacity improvement from MIMO setup. The antenna is integrated with varactor (MA46H120) to tune its operating frequency from 2.35 to 2.55 GHz (ISM band). The antenna has a high isolation level (below -15 dB), and a peak gain of around 2.3 dBi across the tuning frequency range. The agreement between measured and simulated results shows successful performance and characteristics satisfying various MIMO parameters requirements. © 2023 IEEE.

关键词： Substrate integrated waveguides

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RIS assisted Cooperative Computation Offloading for Autonomous Vehicle in Mobile Edge computing 100

RIS assisted Cooperative Computation Offloading for Autonomo...

引用

100th IEEE Vehicular technology conference, VTC 2024-Fall

作者： Saleem, Osama Bin Asif, Awais Ribouh, Soheyb Ashraf, Nouman Qureshi, Hassaan Khaliq Nust Sines Islamabad Pakistan Nust Seecs Islamabad Pakistan University of Rouen Litis Rouen France Technological University Dublin Ireland

ISBN: (纸本)9798331517786

Vehicular networks are a crucial component aimed to revolutionize the transportation system through the integration of several services and technologies including autonomous driving, dynamic routing, real-time traffic monitoring, and onboard entertainment systems. These services necessitate robust computational resources, seamlessly fulfilled by mobile edge computing (MEC) trough the roadside units (RSUs). MEC excels in offering low-latency with real-time data access, which is critical for these applications. As we gear up for the advent of 6G networks, which will operate at millimeter-wave and terahertz frequencies, the challenge of signal loss becomes significant. To this end, this paper propose a novel 6G latency aware computational offloading framework that strategically deploys reconfigurable Intelligent Surfaces (RIS) between autonomous vehicles and RSUs. Our approach leverage cooperative interactions among RSUs, which enhances overall service performance and significantly reduces latency. Both of these factors are crucial for providing efficient MEC environment in vehicular networks. Our proposed method has been implemented and tested where the results shows that our approach achieves 5 to 7 seconds reduction in time delay compared to the state-of-the-art approaches. © 2024 IEEE.

关键词： Autonomous vehicles

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Towards Evidence-Based Cybersecurity Assessment of Programmable Systems to Ensure the Protection of Critical IT Infrastructure 12

Towards Evidence-Based Cybersecurity Assessment of Programma...

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12th IEEE International conference on Intelligent Data Acquisition and Advanced computing Systems: technology and applications, IDAACS 2023

作者： Illiashenko, Oleg Kharchenko, Vyacheslav Odarushchenko, Oleg National Aerospace University 'KhAI' Department of Computer Systems and Networks Kharkiv61070 Ukraine Institute of Information Science and Technologies 'Alessandro Faedo' - Isti Cnr Software Engineering & Dependable Computing Laboratory Pisa56124 Italy Research and Production Enterprise Rpc Radics Llc Kropyvnytskyi25009 Ukraine

ISBN: (纸本)9798350358056

The paper is devoted to developing scientific principles, methods, means, and information technology of model-oriented verification and evidence-based assessment using functional safety and cybersecurity cases for programmable systems of critical applications (PSCA). In particular, information and control systems important for the safety of nuclear power plants (NPPs), aerospace systems, railway domains, etc., developed using Field Programmable Gate Arrays (fpgas) and hardware platforms are reviewed. The goal is to ensure the guaranteed completeness and reliability of its functional safety and cybersecurity assessment by developing and implementing a set of formal and semi-formal methods and tools that consider defects of different nature - physical, design, trojans, and vulnerabilities that can be attacked and lead to a fatal system failure, which results in damaging the critical IT infrastructure. The methods shown are based on integrating algebraic, tabular, graph models, and case assessment methodology. The methods are implemented as appropriate technologies for evidence-based verification and evaluation of PSCA. For formal methods, a prototype of a translator of Very High-Speed Integrated Circuits Hardware Description Language (VHDL) code is developed into an algebra of behaviors. It provides evidence-based verification and a framework and tools to design reports on assessing the cybersecurity and functional safety of programmable systems. © 2023 IEEE.

关键词： critical IT infrastructure cybersecurity FPGA functional safety programmable systems of critical applications

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Frequency reconfigurable Antenna for 5G applications at n77 and n78 Bands 3rd

Frequency Reconfigurable Antenna for 5G Applications at n77 ...

引用

3rd EAI International conference on Cognitive computing and Cyber Physical Systems, IC4S 2022

作者： Orugu, Rangarao Moses, Nesasudha Janapala, Doondi Kumar Karunya Institute of Technology and Sciences Tamilnadu Coimbatore641114 India Vishnu Institute of Technology Andhra Pradesh Bhimavaram534202 India

ISBN: (纸本)9783031289743

A frequency reconfigurable antenna is designed and presented for 5G applications. The proposed antenna is designed by using two T shaped patches positioned inversely to each other and connected by a PIN diode. Here the bottom T shaped patch is inverted and connected to the micro strip line feeding. FR4 substrate is used as dielectric and the backside ground is maintained partial with a rectangular open slot is etched opposite to the feed point. The PIN diode acts as a switch to change the operating frequency of the proposed antenna in-between n77 and n78 bands of 5G applications. The simulated analysis of proposed 5G antenna showed that, when diode is in OFF conditions it operates at 3.5 GHz with operational band covers from 3.34 GHz to 3.7 GHz. Similarly, when diode is in ON condition the antenna operated at 3.7 GHz with operational band covering from 3.47 GHz to 3.94 GHz. The performance of the frequency reconfigurable 5G antenna for OFF and ON conditions is compared with the help of S11 vs frequency, VSWR and radiation pattern curves and presented. The proposed antenna maintained similar radiation coverage at respective resonant frequencies for OFF and ON conditions making it suitable for future 5G applications. © 2023, ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering.

关键词： Natural frequencies

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Performance Evaluation of RIS under Different Wireless Communication Standards and Channel Models 2

Performance Evaluation of RIS under Different Wireless Commu...

引用

2nd International conference on Edge computing and applications, ICECAA 2023

作者： Krishna Teja Yadav, C.H.T. Venkateswaran, K. Srivastava, Ashutosh Cmr Institute of Technology Department of Electronics & Communication Engineering Bengaluru India

ISBN: (纸本)9798350347579

reconfigurable Intelligent Surface (RIS) technology has gained immense popularity as an innovative solution for enhancing wireless communication systems. The RIS consists of multiple reflecting elements which are controlled in a passive manner so as to reflect the incoming signal in a particular direction. This study performs simulation to evaluate the performance of RIS-based wireless communication systems under various communication standards and channel models. Here a single element's reflection coefficient is selected as a constant value and a randomly generated positions of the transmitter and receiver are obtained. Two communication standards, namely 5G and Wi-Fi, and two channel models, Rayleigh and Rician, are considered. The channel gains are computed for each position and presented in a 3D plot with color-coded markers indicating its gain. Finally this simulation facilitates a better understanding of the effect of different wireless communication standards and channel models on the performance of RIS and thus enabling the necessity of numerous optimization techniques in RIS assisted wireless communication systems. © 2023 IEEE.

关键词： Wi-Fi

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NVSystolic: Heterogeneous Simulation Framework for Emerging Memories with Systolic Array 19

NVSystolic: Heterogeneous Simulation Framework for Emerging ...

引用

19th International conference on Synthesis, Modeling, Analysis and Simulation Methods, and applications to Circuit Design, SMACD 2023

作者： Chithambara Moorthii, J. Khanv, Sufyan Suri, Manan Indian Institute of Technology Delhi New Delhi India

ISBN: (纸本)9798350332650

In recent years, hardware accelerators have shown significant advantages in the field of deep neural networks. The architecture used in such systems has high memory utilization. To make the most of memory technology in conjunction with compute fabric, careful study of memory optimisation is thus necessary. NVSystolic, a heterogeneous simulation framework based on reconfigurable memory subsystems with a systolic array serving as the computing unit, is presented in this study. In particular, Non-Volatile Memory (NVM) can be modelled by the framework for the systolic array-based accelerator. © 2023 IEEE.

关键词： Systolic arrays

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FPGA accelerated DeepSORT object tracking 24

FPGA accelerated DeepSORT object tracking

引用

24th International Carpathian Control conference, ICCC 2023

作者： Szanto, Peter Kiss, Tamas Sipos, Karoly Janos Budapest University of Technology and Economics Department of Measurement and Information Systems Budapest Hungary

ISBN: (纸本)9798350310221

Object detection and tracking is one of the most important vision algorithms in intelligent environments, applications based on it are the driving force behind the growing deployment of edge devices. As fpgas can implement application specific hardware accelerators, they not only offer outstanding performance but also increased energy efficiency which is a very important factor in edge devices and the most recent FPGA families include processing elements which greatly increase the efficiency and performance of AI inference. In this paper we present a heterogeneous FPGA based implementation of the popular DeepSORT tracking algorithm. © 2023 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Dimensionality Reduction of Sparse Wireless Channel Based on Spatial Geometrical Structure of RIS Assisted Communication System 5

Dimensionality Reduction of Sparse Wireless Channel Based on...

引用

5th International conference on Inventive Research in computing applications, ICIRCA 2023

作者： Yadav Ch T, Krishna Teja Venkateswaran, K. Cmr Institute of Technology Department of Electronics & Communication Bengaluru India

ISBN: (纸本)9798350321425

reconfigurable Intelligent Surfaces (RIS) makes the channel more controllable by manipulating the propagation environment, so that wireless medium becomes smart when compared to conventional wireless communication system. In this study dataset from SPCUP 2021 is considered for a communication system involving two dimensional RIS consisting of NV reflecting elements vertically and NH elements horizontally each operating in binary state. When operating with fewer number of configurations the system becomes underdetermined which makes it difficult to estimate channel based on received signals. Hence it is required to reduce the dimension in the channel by finding the spatial geometry of RIS depending upon the similarities in the channel coefficients. Based on the simulations carried out in MATLAB it is concluded that square geometry (NV=NH)) is more preferable compared to rectangular geometry (NV\neq NH) since it exhibits periodicity in the channel coefficient. © 2023 IEEE.

关键词： Geometry

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Proceedings of the 12th International Symposium on Highly Efficient Accelerators and reconfigurable Technologies, HEART 2022

Proceedings of the 12th International Symposium on Highly Ef...

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12th International Symposium on Highly Efficient Accelerators and reconfigurable Technologies, HEART 2022

ISBN: (纸本)9781450396608

The proceedings contain 18 papers. The topics discussed include: performance evaluation on GPU-FPGA accelerated computing considering interconnections between accelerators;verifying hardware optimizations for efficient acceleration;accelerating decision tree ensemble with guided branch approximation;a hardware/software co-design approach to prototype 6G mobile applications inside the GNU radio SDR ecosystem using FPGA hardware accelerators;meta-programming design-flow patterns for automating reusable optimizations;a single-source C++20 HLS flow for function evaluation on FPGA and beyond;memory and energy efficient memory model and instruction set architectures for tree data structures;stream computation of 3D approximate convex hulls with an FPGA;and FPGA-dedicated network vs. server network for pipelined computing with multiple fpgas.

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SCRA: Systolic-Friendly DNN Compression and reconfigurable Accelerator Co-Design 21

SCRA: Systolic-Friendly DNN Compression and Reconfigurable A...

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21st IEEE International Symposium on Parallel and Distributed Processing with applications, 13th IEEE International conference on Big Data and Cloud computing, 16th IEEE International conference on Social computing and Networking and 13th International conference on Sustainable computing and Communications, ISPA/BDCloud/SocialCom/SustainCom 2023

作者： Zhang, Xun Wang, ChengLiang Piao, Xingquan Ren, Ao Huang, Zhetong Chongqing University College of Computer Science Chongqing400044 China

ISBN: (纸本)9798350329223

Pruning has become an extremely powerful and effective technique to compress and accelerate sophisticated deep neural networks on resource-constrained platforms. Existing pruning and quantization methods aim to reduce parameter size and computation while maintaining accuracy. However, it is impractical to ignore hardware implementation when focusing on the accuracy of DNNs through pruning and quantization strategies. Moreover, a reduction in computational size does not necessarily result in an increase in inference *** order to strike a balance between DNN accuracy, inference efficiency, and hardware implementation, we propose SCRA, an efficient algorithm-architecture co-design that leverages stripe-based structured pruning strategy to reduce the data movement and fit the data flow of systolic arrays (SAs). Besides, considering the characteristics of the DSP48E2 in the FPGA, we present a quantization strategy for parallel computation of mixed-precision data, achieving acceleration of mixed-precision DNNs computation. Furthermore, we put forward an accelerator to fully exploit the benefits of the pruning strategy and parallel computation. Experimental results demonstrate that the proposed pruning strategy can achieve higher pruning rates without significant loss in model accuracy, and our accelerator achieves 4.79x speed up compared to the baseline. © 2023 IEEE.

关键词： Systolic arrays

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